[PATCH v4 0/1] drm/xe: Set GT rp min frequency as 1.2GHz default for BMG/CRI

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* [PATCH v4 0/1] drm/xe: Set GT rp min frequency as 1.2GHz default for BMG/CRI
@ 2026-03-26  6:34 Nareshkumar Gollakoti
  2026-03-26  6:34 ` [PATCH v4 1/1] " Nareshkumar Gollakoti
                   ` (3 more replies)
  0 siblings, 4 replies; 7+ messages in thread
From: Nareshkumar Gollakoti @ 2026-03-26  6:34 UTC (permalink / raw)
  To: intel-xe; +Cc: thomas.hellstrom, stuart.summers, Nareshkumar Gollakoti

Performance degradation occurs in multi-BMG GPU configurations 
during Peer-to-Peer transactions when one of the two GPUs remains idle
with no engine activity.
The root cause has been identified as frequency downscaling:
the idle remote GPU reduces its operating frequency to the minimum 400MHz,
which negatively impacts the bandwidth available for P2P transactions 
initiated by the active local GPU.

To address above problem this patch ensures for the platform BMG/CRI
of graphics(GT0) tile.the default GT rp frquency min set as 1.2GHz
to ensure effetive P2P transaction bandwidth.

Frequency boosting improves performance, but at the expense of
power consumption.Note that this change only impacts active frequency,
so idle power consumption should remain the same.

v2:
- Fix Indentation(Thomas)
- Add comment about power impact(Stuart)

v3:(Thomas/Ankur/Matt Roper)
- Add setting frequency to only GT0(Graphics) Tile of BMG/CRI

v4:(Stuart)
- Move WA check to pc_needs_min_freq_change function

Nareshkumar Gollakoti (1):
  drm/xe: Set GT rp min frequency as 1.2GHz default for BMG/CRI

 drivers/gpu/drm/xe/xe_guc_pc.c | 32 ++++++++++++++++++++++++++++++--
 1 file changed, 30 insertions(+), 2 deletions(-)

-- 
2.43.0

^ permalink raw reply	[flat|nested] 7+ messages in thread

* [PATCH v4 1/1] drm/xe: Set GT rp min frequency as 1.2GHz default for BMG/CRI
  2026-03-26  6:34 [PATCH v4 0/1] drm/xe: Set GT rp min frequency as 1.2GHz default for BMG/CRI Nareshkumar Gollakoti
@ 2026-03-26  6:34 ` Nareshkumar Gollakoti
  2026-03-30 18:29   ` Belgaumkar, Vinay
  2026-03-26  6:47 ` ✓ CI.KUnit: success for drm/xe: Set GT rp min frequency as 1.2GHz default for BMG/CRI (rev4) Patchwork
                   ` (2 subsequent siblings)
  3 siblings, 1 reply; 7+ messages in thread
From: Nareshkumar Gollakoti @ 2026-03-26  6:34 UTC (permalink / raw)
  To: intel-xe; +Cc: thomas.hellstrom, stuart.summers, Nareshkumar Gollakoti

 While previously applied only to both tiles GT0(Graphics) and Media(GT1)
 the BMG G21(Battle image) platform via workaround Wa_14022085890,
 this 1.2 GHz minimum is now the default for GT0(Graphics) tile
 of BMG and CRI platforms.

 Setting this frequency floor(1.2GHz) default is critical in multi GPU
 environment for supporting effective Peer-to-Peer(P2P) transactions.

v2:
- Fix Indentation(Thomas)
- Add comment about power impact(Stuart)

v3:(Thomas/Ankur/Matt Roper)
- Add setting frequency to only GT0(Graphics) Tile of BMG/CRI

v4:(Stuart)
- Move WA check to pc_needs_min_freq_change function

Signed-off-by: Nareshkumar Gollakoti <naresh.kumar.g@intel.com>
---
 drivers/gpu/drm/xe/xe_guc_pc.c | 32 ++++++++++++++++++++++++++++++--
 1 file changed, 30 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/xe/xe_guc_pc.c b/drivers/gpu/drm/xe/xe_guc_pc.c
index 5e5495a39a3c..f92feee3592d 100644
--- a/drivers/gpu/drm/xe/xe_guc_pc.c
+++ b/drivers/gpu/drm/xe/xe_guc_pc.c
@@ -856,9 +856,26 @@ void xe_guc_pc_init_early(struct xe_guc_pc *pc)
 	pc_init_fused_rp_values(pc);
 }
 
+static bool pc_needs_min_freq_change(struct xe_guc_pc *pc)
+{
+	struct xe_device *xe = pc_to_xe(pc);
+	struct xe_gt *gt = pc_to_gt(pc);
+
+	if (XE_DEVICE_WA(xe, 14022085890))
+		return true;
+
+	if (xe_gt_is_media_type(gt))
+		return false;
+
+	if (xe->info.platform == XE_BATTLEMAGE ||
+	    xe->info.platform == XE_CRESCENTISLAND)
+		return true;
+
+	return false;
+}
+
 static int pc_adjust_freq_bounds(struct xe_guc_pc *pc)
 {
-	struct xe_tile *tile = gt_to_tile(pc_to_gt(pc));
 	int ret;
 
 	lockdep_assert_held(&pc->freq_lock);
@@ -885,7 +902,18 @@ static int pc_adjust_freq_bounds(struct xe_guc_pc *pc)
 	if (pc_get_min_freq(pc) > pc->rp0_freq)
 		ret = pc_set_min_freq(pc, pc->rp0_freq);
 
-	if (XE_DEVICE_WA(tile_to_xe(tile), 14022085890))
+	/*
+	 * Setting GT RP min frequency to 1.2GHz by default for
+	 * GT0(Graphics) Tile of BMG and CRI.
+	 *
+	 * While BMG G21 WA will apply min frequency for
+	 * both GT0(Graphics) and GT1(Media) Tile.
+	 *
+	 * This is an active frequency, so if the device is idle
+	 * we aren't expecting high power output across board
+	 *
+	 */
+	if (pc_needs_min_freq_change(pc))
 		ret = pc_set_min_freq(pc, max(BMG_MIN_FREQ, pc_get_min_freq(pc)));
 
 out:
-- 
2.43.0


^ permalink raw reply related	[flat|nested] 7+ messages in thread

* Re: [PATCH v4 1/1] drm/xe: Set GT rp min frequency as 1.2GHz default for BMG/CRI
  2026-03-26  6:34 ` [PATCH v4 1/1] " Nareshkumar Gollakoti
@ 2026-03-30 18:29   ` Belgaumkar, Vinay
  0 siblings, 0 replies; 7+ messages in thread
From: Belgaumkar, Vinay @ 2026-03-30 18:29 UTC (permalink / raw)
  To: Nareshkumar Gollakoti, intel-xe; +Cc: thomas.hellstrom, stuart.summers


On 3/25/2026 11:34 PM, Nareshkumar Gollakoti wrote:
>   While previously applied only to both tiles GT0(Graphics) and Media(GT1)
>   the BMG G21(Battle image) platform via workaround Wa_14022085890,
>   this 1.2 GHz minimum is now the default for GT0(Graphics) tile
>   of BMG and CRI platforms.
>
>   Setting this frequency floor(1.2GHz) default is critical in multi GPU
>   environment for supporting effective Peer-to-Peer(P2P) transactions.
>
> v2:
> - Fix Indentation(Thomas)
> - Add comment about power impact(Stuart)
>
> v3:(Thomas/Ankur/Matt Roper)
> - Add setting frequency to only GT0(Graphics) Tile of BMG/CRI
>
> v4:(Stuart)
> - Move WA check to pc_needs_min_freq_change function
>
> Signed-off-by: Nareshkumar Gollakoti <naresh.kumar.g@intel.com>
> ---
>   drivers/gpu/drm/xe/xe_guc_pc.c | 32 ++++++++++++++++++++++++++++++--
>   1 file changed, 30 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/xe/xe_guc_pc.c b/drivers/gpu/drm/xe/xe_guc_pc.c
> index 5e5495a39a3c..f92feee3592d 100644
> --- a/drivers/gpu/drm/xe/xe_guc_pc.c
> +++ b/drivers/gpu/drm/xe/xe_guc_pc.c
> @@ -856,9 +856,26 @@ void xe_guc_pc_init_early(struct xe_guc_pc *pc)
>   	pc_init_fused_rp_values(pc);
>   }
>   
> +static bool pc_needs_min_freq_change(struct xe_guc_pc *pc)
> +{
> +	struct xe_device *xe = pc_to_xe(pc);
> +	struct xe_gt *gt = pc_to_gt(pc);
> +
> +	if (XE_DEVICE_WA(xe, 14022085890))
> +		return true;
> +
> +	if (xe_gt_is_media_type(gt))
> +		return false;
> +
> +	if (xe->info.platform == XE_BATTLEMAGE ||
> +	    xe->info.platform == XE_CRESCENTISLAND)
> +		return true;
> +
> +	return false;
> +}
> +
>   static int pc_adjust_freq_bounds(struct xe_guc_pc *pc)
>   {
> -	struct xe_tile *tile = gt_to_tile(pc_to_gt(pc));
>   	int ret;
>   
>   	lockdep_assert_held(&pc->freq_lock);
> @@ -885,7 +902,18 @@ static int pc_adjust_freq_bounds(struct xe_guc_pc *pc)
>   	if (pc_get_min_freq(pc) > pc->rp0_freq)
>   		ret = pc_set_min_freq(pc, pc->rp0_freq);
>   
> -	if (XE_DEVICE_WA(tile_to_xe(tile), 14022085890))
> +	/*
> +	 * Setting GT RP min frequency to 1.2GHz by default for
> +	 * GT0(Graphics) Tile of BMG and CRI.
> +	 *
> +	 * While BMG G21 WA will apply min frequency for
> +	 * both GT0(Graphics) and GT1(Media) Tile.
> +	 *
> +	 * This is an active frequency, so if the device is idle
> +	 * we aren't expecting high power output across board
> +	 *
> +	 */
> +	if (pc_needs_min_freq_change(pc))
>   		ret = pc_set_min_freq(pc, max(BMG_MIN_FREQ, pc_get_min_freq(pc)));

LGTM,

Reviewed-by: Vinay Belgaumkar <vinay.belgaumkar@intel.com>

>   
>   out:

^ permalink raw reply	[flat|nested] 7+ messages in thread

* ✓ CI.KUnit: success for drm/xe: Set GT rp min frequency as 1.2GHz default for BMG/CRI (rev4)
  2026-03-26  6:34 [PATCH v4 0/1] drm/xe: Set GT rp min frequency as 1.2GHz default for BMG/CRI Nareshkumar Gollakoti
  2026-03-26  6:34 ` [PATCH v4 1/1] " Nareshkumar Gollakoti
@ 2026-03-26  6:47 ` Patchwork
  2026-03-26  7:30 ` ✓ Xe.CI.BAT: " Patchwork
  2026-03-26 18:25 ` ✓ Xe.CI.FULL: " Patchwork
  3 siblings, 0 replies; 7+ messages in thread
From: Patchwork @ 2026-03-26  6:47 UTC (permalink / raw)
  To: Nareshkumar Gollakoti; +Cc: intel-xe

== Series Details ==

Series: drm/xe: Set GT rp min frequency as 1.2GHz default for BMG/CRI (rev4)
URL   : https://patchwork.freedesktop.org/series/161656/
State : success

== Summary ==

+ trap cleanup EXIT
+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/xe/.kunitconfig
[06:46:39] Configuring KUnit Kernel ...
Generating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[06:46:43] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[06:47:14] Starting KUnit Kernel (1/1)...
[06:47:14] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[06:47:14] ================== guc_buf (11 subtests) ===================
[06:47:14] [PASSED] test_smallest
[06:47:14] [PASSED] test_largest
[06:47:14] [PASSED] test_granular
[06:47:14] [PASSED] test_unique
[06:47:14] [PASSED] test_overlap
[06:47:14] [PASSED] test_reusable
[06:47:14] [PASSED] test_too_big
[06:47:14] [PASSED] test_flush
[06:47:14] [PASSED] test_lookup
[06:47:14] [PASSED] test_data
[06:47:14] [PASSED] test_class
[06:47:14] ===================== [PASSED] guc_buf =====================
[06:47:14] =================== guc_dbm (7 subtests) ===================
[06:47:14] [PASSED] test_empty
[06:47:14] [PASSED] test_default
[06:47:14] ======================== test_size  ========================
[06:47:14] [PASSED] 4
[06:47:14] [PASSED] 8
[06:47:14] [PASSED] 32
[06:47:14] [PASSED] 256
[06:47:14] ==================== [PASSED] test_size ====================
[06:47:14] ======================= test_reuse  ========================
[06:47:14] [PASSED] 4
[06:47:14] [PASSED] 8
[06:47:14] [PASSED] 32
[06:47:14] [PASSED] 256
[06:47:14] =================== [PASSED] test_reuse ====================
[06:47:14] =================== test_range_overlap  ====================
[06:47:14] [PASSED] 4
[06:47:14] [PASSED] 8
[06:47:14] [PASSED] 32
[06:47:14] [PASSED] 256
[06:47:14] =============== [PASSED] test_range_overlap ================
[06:47:14] =================== test_range_compact  ====================
[06:47:14] [PASSED] 4
[06:47:14] [PASSED] 8
[06:47:14] [PASSED] 32
[06:47:14] [PASSED] 256
[06:47:14] =============== [PASSED] test_range_compact ================
[06:47:14] ==================== test_range_spare  =====================
[06:47:14] [PASSED] 4
[06:47:14] [PASSED] 8
[06:47:14] [PASSED] 32
[06:47:14] [PASSED] 256
[06:47:14] ================ [PASSED] test_range_spare =================
[06:47:14] ===================== [PASSED] guc_dbm =====================
[06:47:14] =================== guc_idm (6 subtests) ===================
[06:47:15] [PASSED] bad_init
[06:47:15] [PASSED] no_init
[06:47:15] [PASSED] init_fini
[06:47:15] [PASSED] check_used
[06:47:15] [PASSED] check_quota
[06:47:15] [PASSED] check_all
[06:47:15] ===================== [PASSED] guc_idm =====================
[06:47:15] ================== no_relay (3 subtests) ===================
[06:47:15] [PASSED] xe_drops_guc2pf_if_not_ready
[06:47:15] [PASSED] xe_drops_guc2vf_if_not_ready
[06:47:15] [PASSED] xe_rejects_send_if_not_ready
[06:47:15] ==================== [PASSED] no_relay =====================
[06:47:15] ================== pf_relay (14 subtests) ==================
[06:47:15] [PASSED] pf_rejects_guc2pf_too_short
[06:47:15] [PASSED] pf_rejects_guc2pf_too_long
[06:47:15] [PASSED] pf_rejects_guc2pf_no_payload
[06:47:15] [PASSED] pf_fails_no_payload
[06:47:15] [PASSED] pf_fails_bad_origin
[06:47:15] [PASSED] pf_fails_bad_type
[06:47:15] [PASSED] pf_txn_reports_error
[06:47:15] [PASSED] pf_txn_sends_pf2guc
[06:47:15] [PASSED] pf_sends_pf2guc
[06:47:15] [SKIPPED] pf_loopback_nop
[06:47:15] [SKIPPED] pf_loopback_echo
[06:47:15] [SKIPPED] pf_loopback_fail
[06:47:15] [SKIPPED] pf_loopback_busy
[06:47:15] [SKIPPED] pf_loopback_retry
[06:47:15] ==================== [PASSED] pf_relay =====================
[06:47:15] ================== vf_relay (3 subtests) ===================
[06:47:15] [PASSED] vf_rejects_guc2vf_too_short
[06:47:15] [PASSED] vf_rejects_guc2vf_too_long
[06:47:15] [PASSED] vf_rejects_guc2vf_no_payload
[06:47:15] ==================== [PASSED] vf_relay =====================
[06:47:15] ================ pf_gt_config (9 subtests) =================
[06:47:15] [PASSED] fair_contexts_1vf
[06:47:15] [PASSED] fair_doorbells_1vf
[06:47:15] [PASSED] fair_ggtt_1vf
[06:47:15] ====================== fair_vram_1vf  ======================
[06:47:15] [PASSED] 3.50 GiB
[06:47:15] [PASSED] 11.5 GiB
[06:47:15] [PASSED] 15.5 GiB
[06:47:15] [PASSED] 31.5 GiB
[06:47:15] [PASSED] 63.5 GiB
[06:47:15] [PASSED] 1.91 GiB
[06:47:15] ================== [PASSED] fair_vram_1vf ==================
[06:47:15] ================ fair_vram_1vf_admin_only  =================
[06:47:15] [PASSED] 3.50 GiB
[06:47:15] [PASSED] 11.5 GiB
[06:47:15] [PASSED] 15.5 GiB
[06:47:15] [PASSED] 31.5 GiB
[06:47:15] [PASSED] 63.5 GiB
[06:47:15] [PASSED] 1.91 GiB
[06:47:15] ============ [PASSED] fair_vram_1vf_admin_only =============
[06:47:15] ====================== fair_contexts  ======================
[06:47:15] [PASSED] 1 VF
[06:47:15] [PASSED] 2 VFs
[06:47:15] [PASSED] 3 VFs
[06:47:15] [PASSED] 4 VFs
[06:47:15] [PASSED] 5 VFs
[06:47:15] [PASSED] 6 VFs
[06:47:15] [PASSED] 7 VFs
[06:47:15] [PASSED] 8 VFs
[06:47:15] [PASSED] 9 VFs
[06:47:15] [PASSED] 10 VFs
[06:47:15] [PASSED] 11 VFs
[06:47:15] [PASSED] 12 VFs
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[06:47:15] [PASSED] 40 VFs
[06:47:15] [PASSED] 41 VFs
[06:47:15] [PASSED] 42 VFs
[06:47:15] [PASSED] 43 VFs
[06:47:15] [PASSED] 44 VFs
[06:47:15] [PASSED] 45 VFs
[06:47:15] [PASSED] 46 VFs
[06:47:15] [PASSED] 47 VFs
[06:47:15] [PASSED] 48 VFs
[06:47:15] [PASSED] 49 VFs
[06:47:15] [PASSED] 50 VFs
[06:47:15] [PASSED] 51 VFs
[06:47:15] [PASSED] 52 VFs
[06:47:15] [PASSED] 53 VFs
[06:47:15] [PASSED] 54 VFs
[06:47:15] [PASSED] 55 VFs
[06:47:15] [PASSED] 56 VFs
[06:47:15] [PASSED] 57 VFs
[06:47:15] [PASSED] 58 VFs
[06:47:15] [PASSED] 59 VFs
[06:47:15] [PASSED] 60 VFs
[06:47:15] [PASSED] 61 VFs
[06:47:15] [PASSED] 62 VFs
[06:47:15] [PASSED] 63 VFs
[06:47:15] ================== [PASSED] fair_contexts ==================
[06:47:15] ===================== fair_doorbells  ======================
[06:47:15] [PASSED] 1 VF
[06:47:15] [PASSED] 2 VFs
[06:47:15] [PASSED] 3 VFs
[06:47:15] [PASSED] 4 VFs
[06:47:15] [PASSED] 5 VFs
[06:47:15] [PASSED] 6 VFs
[06:47:15] [PASSED] 7 VFs
[06:47:15] [PASSED] 8 VFs
[06:47:15] [PASSED] 9 VFs
[06:47:15] [PASSED] 10 VFs
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[06:47:15] [PASSED] 39 VFs
[06:47:15] [PASSED] 40 VFs
[06:47:15] [PASSED] 41 VFs
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[06:47:15] [PASSED] 43 VFs
[06:47:15] [PASSED] 44 VFs
[06:47:15] [PASSED] 45 VFs
[06:47:15] [PASSED] 46 VFs
[06:47:15] [PASSED] 47 VFs
[06:47:15] [PASSED] 48 VFs
[06:47:15] [PASSED] 49 VFs
[06:47:15] [PASSED] 50 VFs
[06:47:15] [PASSED] 51 VFs
[06:47:15] [PASSED] 52 VFs
[06:47:15] [PASSED] 53 VFs
[06:47:15] [PASSED] 54 VFs
[06:47:15] [PASSED] 55 VFs
[06:47:15] [PASSED] 56 VFs
[06:47:15] [PASSED] 57 VFs
[06:47:15] [PASSED] 58 VFs
[06:47:15] [PASSED] 59 VFs
[06:47:15] [PASSED] 60 VFs
[06:47:15] [PASSED] 61 VFs
[06:47:15] [PASSED] 62 VFs
[06:47:15] [PASSED] 63 VFs
[06:47:15] ================= [PASSED] fair_doorbells ==================
[06:47:15] ======================== fair_ggtt  ========================
[06:47:15] [PASSED] 1 VF
[06:47:15] [PASSED] 2 VFs
[06:47:15] [PASSED] 3 VFs
[06:47:15] [PASSED] 4 VFs
[06:47:15] [PASSED] 5 VFs
[06:47:15] [PASSED] 6 VFs
[06:47:15] [PASSED] 7 VFs
[06:47:15] [PASSED] 8 VFs
[06:47:15] [PASSED] 9 VFs
[06:47:15] [PASSED] 10 VFs
[06:47:15] [PASSED] 11 VFs
[06:47:15] [PASSED] 12 VFs
[06:47:15] [PASSED] 13 VFs
[06:47:15] [PASSED] 14 VFs
[06:47:15] [PASSED] 15 VFs
[06:47:15] [PASSED] 16 VFs
[06:47:15] [PASSED] 17 VFs
[06:47:15] [PASSED] 18 VFs
[06:47:15] [PASSED] 19 VFs
[06:47:15] [PASSED] 20 VFs
[06:47:15] [PASSED] 21 VFs
[06:47:15] [PASSED] 22 VFs
[06:47:15] [PASSED] 23 VFs
[06:47:15] [PASSED] 24 VFs
[06:47:15] [PASSED] 25 VFs
[06:47:15] [PASSED] 26 VFs
[06:47:15] [PASSED] 27 VFs
[06:47:15] [PASSED] 28 VFs
[06:47:15] [PASSED] 29 VFs
[06:47:15] [PASSED] 30 VFs
[06:47:15] [PASSED] 31 VFs
[06:47:15] [PASSED] 32 VFs
[06:47:15] [PASSED] 33 VFs
[06:47:15] [PASSED] 34 VFs
[06:47:15] [PASSED] 35 VFs
[06:47:15] [PASSED] 36 VFs
[06:47:15] [PASSED] 37 VFs
[06:47:15] [PASSED] 38 VFs
[06:47:15] [PASSED] 39 VFs
[06:47:15] [PASSED] 40 VFs
[06:47:15] [PASSED] 41 VFs
[06:47:15] [PASSED] 42 VFs
[06:47:15] [PASSED] 43 VFs
[06:47:15] [PASSED] 44 VFs
[06:47:15] [PASSED] 45 VFs
[06:47:15] [PASSED] 46 VFs
[06:47:15] [PASSED] 47 VFs
[06:47:15] [PASSED] 48 VFs
[06:47:15] [PASSED] 49 VFs
[06:47:15] [PASSED] 50 VFs
[06:47:15] [PASSED] 51 VFs
[06:47:15] [PASSED] 52 VFs
[06:47:15] [PASSED] 53 VFs
[06:47:15] [PASSED] 54 VFs
[06:47:15] [PASSED] 55 VFs
[06:47:15] [PASSED] 56 VFs
[06:47:15] [PASSED] 57 VFs
[06:47:15] [PASSED] 58 VFs
[06:47:15] [PASSED] 59 VFs
[06:47:15] [PASSED] 60 VFs
[06:47:15] [PASSED] 61 VFs
[06:47:15] [PASSED] 62 VFs
[06:47:15] [PASSED] 63 VFs
[06:47:15] ==================== [PASSED] fair_ggtt ====================
[06:47:15] ======================== fair_vram  ========================
[06:47:15] [PASSED] 1 VF
[06:47:15] [PASSED] 2 VFs
[06:47:15] [PASSED] 3 VFs
[06:47:15] [PASSED] 4 VFs
[06:47:15] [PASSED] 5 VFs
[06:47:15] [PASSED] 6 VFs
[06:47:15] [PASSED] 7 VFs
[06:47:15] [PASSED] 8 VFs
[06:47:15] [PASSED] 9 VFs
[06:47:15] [PASSED] 10 VFs
[06:47:15] [PASSED] 11 VFs
[06:47:15] [PASSED] 12 VFs
[06:47:15] [PASSED] 13 VFs
[06:47:15] [PASSED] 14 VFs
[06:47:15] [PASSED] 15 VFs
[06:47:15] [PASSED] 16 VFs
[06:47:15] [PASSED] 17 VFs
[06:47:15] [PASSED] 18 VFs
[06:47:15] [PASSED] 19 VFs
[06:47:15] [PASSED] 20 VFs
[06:47:15] [PASSED] 21 VFs
[06:47:15] [PASSED] 22 VFs
[06:47:15] [PASSED] 23 VFs
[06:47:15] [PASSED] 24 VFs
[06:47:15] [PASSED] 25 VFs
[06:47:15] [PASSED] 26 VFs
[06:47:15] [PASSED] 27 VFs
[06:47:15] [PASSED] 28 VFs
[06:47:15] [PASSED] 29 VFs
[06:47:15] [PASSED] 30 VFs
[06:47:15] [PASSED] 31 VFs
[06:47:15] [PASSED] 32 VFs
[06:47:15] [PASSED] 33 VFs
[06:47:15] [PASSED] 34 VFs
[06:47:15] [PASSED] 35 VFs
[06:47:15] [PASSED] 36 VFs
[06:47:15] [PASSED] 37 VFs
[06:47:15] [PASSED] 38 VFs
[06:47:15] [PASSED] 39 VFs
[06:47:15] [PASSED] 40 VFs
[06:47:15] [PASSED] 41 VFs
[06:47:15] [PASSED] 42 VFs
[06:47:15] [PASSED] 43 VFs
[06:47:15] [PASSED] 44 VFs
[06:47:15] [PASSED] 45 VFs
[06:47:15] [PASSED] 46 VFs
[06:47:15] [PASSED] 47 VFs
[06:47:15] [PASSED] 48 VFs
[06:47:15] [PASSED] 49 VFs
[06:47:15] [PASSED] 50 VFs
[06:47:15] [PASSED] 51 VFs
[06:47:15] [PASSED] 52 VFs
[06:47:15] [PASSED] 53 VFs
[06:47:15] [PASSED] 54 VFs
[06:47:15] [PASSED] 55 VFs
[06:47:15] [PASSED] 56 VFs
[06:47:15] [PASSED] 57 VFs
[06:47:15] [PASSED] 58 VFs
[06:47:15] [PASSED] 59 VFs
[06:47:15] [PASSED] 60 VFs
[06:47:15] [PASSED] 61 VFs
[06:47:15] [PASSED] 62 VFs
[06:47:15] [PASSED] 63 VFs
[06:47:15] ==================== [PASSED] fair_vram ====================
[06:47:15] ================== [PASSED] pf_gt_config ===================
[06:47:15] ===================== lmtt (1 subtest) =====================
[06:47:15] ======================== test_ops  =========================
[06:47:15] [PASSED] 2-level
[06:47:15] [PASSED] multi-level
[06:47:15] ==================== [PASSED] test_ops =====================
[06:47:15] ====================== [PASSED] lmtt =======================
[06:47:15] ================= pf_service (11 subtests) =================
[06:47:15] [PASSED] pf_negotiate_any
[06:47:15] [PASSED] pf_negotiate_base_match
[06:47:15] [PASSED] pf_negotiate_base_newer
[06:47:15] [PASSED] pf_negotiate_base_next
[06:47:15] [SKIPPED] pf_negotiate_base_older
[06:47:15] [PASSED] pf_negotiate_base_prev
[06:47:15] [PASSED] pf_negotiate_latest_match
[06:47:15] [PASSED] pf_negotiate_latest_newer
[06:47:15] [PASSED] pf_negotiate_latest_next
[06:47:15] [SKIPPED] pf_negotiate_latest_older
[06:47:15] [SKIPPED] pf_negotiate_latest_prev
[06:47:15] =================== [PASSED] pf_service ====================
[06:47:15] ================= xe_guc_g2g (2 subtests) ==================
[06:47:15] ============== xe_live_guc_g2g_kunit_default  ==============
[06:47:15] ========= [SKIPPED] xe_live_guc_g2g_kunit_default ==========
[06:47:15] ============== xe_live_guc_g2g_kunit_allmem  ===============
[06:47:15] ========== [SKIPPED] xe_live_guc_g2g_kunit_allmem ==========
[06:47:15] =================== [SKIPPED] xe_guc_g2g ===================
[06:47:15] =================== xe_mocs (2 subtests) ===================
[06:47:15] ================ xe_live_mocs_kernel_kunit  ================
[06:47:15] =========== [SKIPPED] xe_live_mocs_kernel_kunit ============
[06:47:15] ================ xe_live_mocs_reset_kunit  =================
[06:47:15] ============ [SKIPPED] xe_live_mocs_reset_kunit ============
[06:47:15] ==================== [SKIPPED] xe_mocs =====================
[06:47:15] ================= xe_migrate (2 subtests) ==================
[06:47:15] ================= xe_migrate_sanity_kunit  =================
[06:47:15] ============ [SKIPPED] xe_migrate_sanity_kunit =============
[06:47:15] ================== xe_validate_ccs_kunit  ==================
[06:47:15] ============= [SKIPPED] xe_validate_ccs_kunit ==============
[06:47:15] =================== [SKIPPED] xe_migrate ===================
[06:47:15] ================== xe_dma_buf (1 subtest) ==================
[06:47:15] ==================== xe_dma_buf_kunit  =====================
[06:47:15] ================ [SKIPPED] xe_dma_buf_kunit ================
[06:47:15] =================== [SKIPPED] xe_dma_buf ===================
[06:47:15] ================= xe_bo_shrink (1 subtest) =================
[06:47:15] =================== xe_bo_shrink_kunit  ====================
[06:47:15] =============== [SKIPPED] xe_bo_shrink_kunit ===============
[06:47:15] ================== [SKIPPED] xe_bo_shrink ==================
[06:47:15] ==================== xe_bo (2 subtests) ====================
[06:47:15] ================== xe_ccs_migrate_kunit  ===================
[06:47:15] ============== [SKIPPED] xe_ccs_migrate_kunit ==============
[06:47:15] ==================== xe_bo_evict_kunit  ====================
[06:47:15] =============== [SKIPPED] xe_bo_evict_kunit ================
[06:47:15] ===================== [SKIPPED] xe_bo ======================
[06:47:15] ==================== args (13 subtests) ====================
[06:47:15] [PASSED] count_args_test
[06:47:15] [PASSED] call_args_example
[06:47:15] [PASSED] call_args_test
[06:47:15] [PASSED] drop_first_arg_example
[06:47:15] [PASSED] drop_first_arg_test
[06:47:15] [PASSED] first_arg_example
[06:47:15] [PASSED] first_arg_test
[06:47:15] [PASSED] last_arg_example
[06:47:15] [PASSED] last_arg_test
[06:47:15] [PASSED] pick_arg_example
[06:47:15] [PASSED] if_args_example
[06:47:15] [PASSED] if_args_test
[06:47:15] [PASSED] sep_comma_example
[06:47:15] ====================== [PASSED] args =======================
[06:47:15] =================== xe_pci (3 subtests) ====================
[06:47:15] ==================== check_graphics_ip  ====================
[06:47:15] [PASSED] 12.00 Xe_LP
[06:47:15] [PASSED] 12.10 Xe_LP+
[06:47:15] [PASSED] 12.55 Xe_HPG
[06:47:15] [PASSED] 12.60 Xe_HPC
[06:47:15] [PASSED] 12.70 Xe_LPG
[06:47:15] [PASSED] 12.71 Xe_LPG
[06:47:15] [PASSED] 12.74 Xe_LPG+
[06:47:15] [PASSED] 20.01 Xe2_HPG
[06:47:15] [PASSED] 20.02 Xe2_HPG
[06:47:15] [PASSED] 20.04 Xe2_LPG
[06:47:15] [PASSED] 30.00 Xe3_LPG
[06:47:15] [PASSED] 30.01 Xe3_LPG
[06:47:15] [PASSED] 30.03 Xe3_LPG
[06:47:15] [PASSED] 30.04 Xe3_LPG
[06:47:15] [PASSED] 30.05 Xe3_LPG
[06:47:15] [PASSED] 35.10 Xe3p_LPG
[06:47:15] [PASSED] 35.11 Xe3p_XPC
[06:47:15] ================ [PASSED] check_graphics_ip ================
[06:47:15] ===================== check_media_ip  ======================
[06:47:15] [PASSED] 12.00 Xe_M
[06:47:15] [PASSED] 12.55 Xe_HPM
[06:47:15] [PASSED] 13.00 Xe_LPM+
[06:47:15] [PASSED] 13.01 Xe2_HPM
[06:47:15] [PASSED] 20.00 Xe2_LPM
[06:47:15] [PASSED] 30.00 Xe3_LPM
[06:47:15] [PASSED] 30.02 Xe3_LPM
[06:47:15] [PASSED] 35.00 Xe3p_LPM
[06:47:15] [PASSED] 35.03 Xe3p_HPM
[06:47:15] ================= [PASSED] check_media_ip ==================
[06:47:15] =================== check_platform_desc  ===================
[06:47:15] [PASSED] 0x9A60 (TIGERLAKE)
[06:47:15] [PASSED] 0x9A68 (TIGERLAKE)
[06:47:15] [PASSED] 0x9A70 (TIGERLAKE)
[06:47:15] [PASSED] 0x9A40 (TIGERLAKE)
[06:47:15] [PASSED] 0x9A49 (TIGERLAKE)
[06:47:15] [PASSED] 0x9A59 (TIGERLAKE)
[06:47:15] [PASSED] 0x9A78 (TIGERLAKE)
[06:47:15] [PASSED] 0x9AC0 (TIGERLAKE)
[06:47:15] [PASSED] 0x9AC9 (TIGERLAKE)
[06:47:15] [PASSED] 0x9AD9 (TIGERLAKE)
[06:47:15] [PASSED] 0x9AF8 (TIGERLAKE)
[06:47:15] [PASSED] 0x4C80 (ROCKETLAKE)
[06:47:15] [PASSED] 0x4C8A (ROCKETLAKE)
[06:47:15] [PASSED] 0x4C8B (ROCKETLAKE)
[06:47:15] [PASSED] 0x4C8C (ROCKETLAKE)
[06:47:15] [PASSED] 0x4C90 (ROCKETLAKE)
[06:47:15] [PASSED] 0x4C9A (ROCKETLAKE)
[06:47:15] [PASSED] 0x4680 (ALDERLAKE_S)
[06:47:15] [PASSED] 0x4682 (ALDERLAKE_S)
[06:47:15] [PASSED] 0x4688 (ALDERLAKE_S)
[06:47:15] [PASSED] 0x468A (ALDERLAKE_S)
[06:47:15] [PASSED] 0x468B (ALDERLAKE_S)
[06:47:15] [PASSED] 0x4690 (ALDERLAKE_S)
[06:47:15] [PASSED] 0x4692 (ALDERLAKE_S)
[06:47:15] [PASSED] 0x4693 (ALDERLAKE_S)
[06:47:15] [PASSED] 0x46A0 (ALDERLAKE_P)
[06:47:15] [PASSED] 0x46A1 (ALDERLAKE_P)
[06:47:15] [PASSED] 0x46A2 (ALDERLAKE_P)
[06:47:15] [PASSED] 0x46A3 (ALDERLAKE_P)
[06:47:15] [PASSED] 0x46A6 (ALDERLAKE_P)
[06:47:15] [PASSED] 0x46A8 (ALDERLAKE_P)
[06:47:15] [PASSED] 0x46AA (ALDERLAKE_P)
[06:47:15] [PASSED] 0x462A (ALDERLAKE_P)
[06:47:15] [PASSED] 0x4626 (ALDERLAKE_P)
[06:47:15] [PASSED] 0x4628 (ALDERLAKE_P)
[06:47:15] [PASSED] 0x46B0 (ALDERLAKE_P)
[06:47:15] [PASSED] 0x46B1 (ALDERLAKE_P)
[06:47:15] [PASSED] 0x46B2 (ALDERLAKE_P)
[06:47:15] [PASSED] 0x46B3 (ALDERLAKE_P)
[06:47:15] [PASSED] 0x46C0 (ALDERLAKE_P)
[06:47:15] [PASSED] 0x46C1 (ALDERLAKE_P)
[06:47:15] [PASSED] 0x46C2 (ALDERLAKE_P)
[06:47:15] [PASSED] 0x46C3 (ALDERLAKE_P)
[06:47:15] [PASSED] 0x46D0 (ALDERLAKE_N)
[06:47:15] [PASSED] 0x46D1 (ALDERLAKE_N)
[06:47:15] [PASSED] 0x46D2 (ALDERLAKE_N)
[06:47:15] [PASSED] 0x46D3 (ALDERLAKE_N)
[06:47:15] [PASSED] 0x46D4 (ALDERLAKE_N)
[06:47:15] [PASSED] 0xA721 (ALDERLAKE_P)
[06:47:15] [PASSED] 0xA7A1 (ALDERLAKE_P)
[06:47:15] [PASSED] 0xA7A9 (ALDERLAKE_P)
[06:47:15] [PASSED] 0xA7AC (ALDERLAKE_P)
[06:47:15] [PASSED] 0xA7AD (ALDERLAKE_P)
[06:47:15] [PASSED] 0xA720 (ALDERLAKE_P)
[06:47:15] [PASSED] 0xA7A0 (ALDERLAKE_P)
[06:47:15] [PASSED] 0xA7A8 (ALDERLAKE_P)
[06:47:15] [PASSED] 0xA7AA (ALDERLAKE_P)
[06:47:15] [PASSED] 0xA7AB (ALDERLAKE_P)
[06:47:15] [PASSED] 0xA780 (ALDERLAKE_S)
[06:47:15] [PASSED] 0xA781 (ALDERLAKE_S)
[06:47:15] [PASSED] 0xA782 (ALDERLAKE_S)
[06:47:15] [PASSED] 0xA783 (ALDERLAKE_S)
[06:47:15] [PASSED] 0xA788 (ALDERLAKE_S)
[06:47:15] [PASSED] 0xA789 (ALDERLAKE_S)
[06:47:15] [PASSED] 0xA78A (ALDERLAKE_S)
[06:47:15] [PASSED] 0xA78B (ALDERLAKE_S)
[06:47:15] [PASSED] 0x4905 (DG1)
[06:47:15] [PASSED] 0x4906 (DG1)
[06:47:15] [PASSED] 0x4907 (DG1)
[06:47:15] [PASSED] 0x4908 (DG1)
[06:47:15] [PASSED] 0x4909 (DG1)
[06:47:15] [PASSED] 0x56C0 (DG2)
[06:47:15] [PASSED] 0x56C2 (DG2)
[06:47:15] [PASSED] 0x56C1 (DG2)
[06:47:15] [PASSED] 0x7D51 (METEORLAKE)
[06:47:15] [PASSED] 0x7DD1 (METEORLAKE)
[06:47:15] [PASSED] 0x7D41 (METEORLAKE)
[06:47:15] [PASSED] 0x7D67 (METEORLAKE)
[06:47:15] [PASSED] 0xB640 (METEORLAKE)
[06:47:15] [PASSED] 0x56A0 (DG2)
[06:47:15] [PASSED] 0x56A1 (DG2)
[06:47:15] [PASSED] 0x56A2 (DG2)
[06:47:15] [PASSED] 0x56BE (DG2)
[06:47:15] [PASSED] 0x56BF (DG2)
[06:47:15] [PASSED] 0x5690 (DG2)
[06:47:15] [PASSED] 0x5691 (DG2)
[06:47:15] [PASSED] 0x5692 (DG2)
[06:47:15] [PASSED] 0x56A5 (DG2)
[06:47:15] [PASSED] 0x56A6 (DG2)
[06:47:15] [PASSED] 0x56B0 (DG2)
[06:47:15] [PASSED] 0x56B1 (DG2)
[06:47:15] [PASSED] 0x56BA (DG2)
[06:47:15] [PASSED] 0x56BB (DG2)
[06:47:15] [PASSED] 0x56BC (DG2)
[06:47:15] [PASSED] 0x56BD (DG2)
[06:47:15] [PASSED] 0x5693 (DG2)
[06:47:15] [PASSED] 0x5694 (DG2)
[06:47:15] [PASSED] 0x5695 (DG2)
[06:47:15] [PASSED] 0x56A3 (DG2)
[06:47:15] [PASSED] 0x56A4 (DG2)
[06:47:15] [PASSED] 0x56B2 (DG2)
[06:47:15] [PASSED] 0x56B3 (DG2)
[06:47:15] [PASSED] 0x5696 (DG2)
[06:47:15] [PASSED] 0x5697 (DG2)
[06:47:15] [PASSED] 0xB69 (PVC)
[06:47:15] [PASSED] 0xB6E (PVC)
[06:47:15] [PASSED] 0xBD4 (PVC)
[06:47:15] [PASSED] 0xBD5 (PVC)
[06:47:15] [PASSED] 0xBD6 (PVC)
[06:47:15] [PASSED] 0xBD7 (PVC)
[06:47:15] [PASSED] 0xBD8 (PVC)
[06:47:15] [PASSED] 0xBD9 (PVC)
[06:47:15] [PASSED] 0xBDA (PVC)
[06:47:15] [PASSED] 0xBDB (PVC)
[06:47:15] [PASSED] 0xBE0 (PVC)
[06:47:15] [PASSED] 0xBE1 (PVC)
[06:47:15] [PASSED] 0xBE5 (PVC)
[06:47:15] [PASSED] 0x7D40 (METEORLAKE)
[06:47:15] [PASSED] 0x7D45 (METEORLAKE)
[06:47:15] [PASSED] 0x7D55 (METEORLAKE)
[06:47:15] [PASSED] 0x7D60 (METEORLAKE)
[06:47:15] [PASSED] 0x7DD5 (METEORLAKE)
[06:47:15] [PASSED] 0x6420 (LUNARLAKE)
[06:47:15] [PASSED] 0x64A0 (LUNARLAKE)
[06:47:15] [PASSED] 0x64B0 (LUNARLAKE)
[06:47:15] [PASSED] 0xE202 (BATTLEMAGE)
[06:47:15] [PASSED] 0xE209 (BATTLEMAGE)
[06:47:15] [PASSED] 0xE20B (BATTLEMAGE)
[06:47:15] [PASSED] 0xE20C (BATTLEMAGE)
[06:47:15] [PASSED] 0xE20D (BATTLEMAGE)
[06:47:15] [PASSED] 0xE210 (BATTLEMAGE)
[06:47:15] [PASSED] 0xE211 (BATTLEMAGE)
[06:47:15] [PASSED] 0xE212 (BATTLEMAGE)
[06:47:15] [PASSED] 0xE216 (BATTLEMAGE)
[06:47:15] [PASSED] 0xE220 (BATTLEMAGE)
[06:47:15] [PASSED] 0xE221 (BATTLEMAGE)
[06:47:15] [PASSED] 0xE222 (BATTLEMAGE)
[06:47:15] [PASSED] 0xE223 (BATTLEMAGE)
[06:47:15] [PASSED] 0xB080 (PANTHERLAKE)
[06:47:15] [PASSED] 0xB081 (PANTHERLAKE)
[06:47:15] [PASSED] 0xB082 (PANTHERLAKE)
[06:47:15] [PASSED] 0xB083 (PANTHERLAKE)
[06:47:15] [PASSED] 0xB084 (PANTHERLAKE)
[06:47:15] [PASSED] 0xB085 (PANTHERLAKE)
[06:47:15] [PASSED] 0xB086 (PANTHERLAKE)
[06:47:15] [PASSED] 0xB087 (PANTHERLAKE)
[06:47:15] [PASSED] 0xB08F (PANTHERLAKE)
[06:47:15] [PASSED] 0xB090 (PANTHERLAKE)
[06:47:15] [PASSED] 0xB0A0 (PANTHERLAKE)
[06:47:15] [PASSED] 0xB0B0 (PANTHERLAKE)
[06:47:15] [PASSED] 0xFD80 (PANTHERLAKE)
[06:47:15] [PASSED] 0xFD81 (PANTHERLAKE)
[06:47:15] [PASSED] 0xD740 (NOVALAKE_S)
[06:47:15] [PASSED] 0xD741 (NOVALAKE_S)
[06:47:15] [PASSED] 0xD742 (NOVALAKE_S)
[06:47:15] [PASSED] 0xD743 (NOVALAKE_S)
[06:47:15] [PASSED] 0xD744 (NOVALAKE_S)
[06:47:15] [PASSED] 0xD745 (NOVALAKE_S)
[06:47:15] [PASSED] 0x674C (CRESCENTISLAND)
[06:47:15] [PASSED] 0xD750 (NOVALAKE_P)
[06:47:15] [PASSED] 0xD751 (NOVALAKE_P)
[06:47:15] [PASSED] 0xD752 (NOVALAKE_P)
[06:47:15] [PASSED] 0xD753 (NOVALAKE_P)
[06:47:15] [PASSED] 0xD754 (NOVALAKE_P)
[06:47:15] [PASSED] 0xD755 (NOVALAKE_P)
[06:47:15] [PASSED] 0xD756 (NOVALAKE_P)
[06:47:15] [PASSED] 0xD757 (NOVALAKE_P)
[06:47:15] [PASSED] 0xD75F (NOVALAKE_P)
[06:47:15] =============== [PASSED] check_platform_desc ===============
[06:47:15] ===================== [PASSED] xe_pci ======================
[06:47:15] =================== xe_rtp (2 subtests) ====================
[06:47:15] =============== xe_rtp_process_to_sr_tests  ================
[06:47:15] [PASSED] coalesce-same-reg
[06:47:15] [PASSED] no-match-no-add
[06:47:15] [PASSED] match-or
[06:47:15] [PASSED] match-or-xfail
[06:47:15] [PASSED] no-match-no-add-multiple-rules
[06:47:15] [PASSED] two-regs-two-entries
[06:47:15] [PASSED] clr-one-set-other
[06:47:15] [PASSED] set-field
[06:47:15] [PASSED] conflict-duplicate
stty: 'standard input': Inappropriate ioctl for device
[06:47:15] [PASSED] conflict-not-disjoint
[06:47:15] [PASSED] conflict-reg-type
[06:47:15] =========== [PASSED] xe_rtp_process_to_sr_tests ============
[06:47:15] ================== xe_rtp_process_tests  ===================
[06:47:15] [PASSED] active1
[06:47:15] [PASSED] active2
[06:47:15] [PASSED] active-inactive
[06:47:15] [PASSED] inactive-active
[06:47:15] [PASSED] inactive-1st_or_active-inactive
[06:47:15] [PASSED] inactive-2nd_or_active-inactive
[06:47:15] [PASSED] inactive-last_or_active-inactive
[06:47:15] [PASSED] inactive-no_or_active-inactive
[06:47:15] ============== [PASSED] xe_rtp_process_tests ===============
[06:47:15] ===================== [PASSED] xe_rtp ======================
[06:47:15] ==================== xe_wa (1 subtest) =====================
[06:47:15] ======================== xe_wa_gt  =========================
[06:47:15] [PASSED] TIGERLAKE B0
[06:47:15] [PASSED] DG1 A0
[06:47:15] [PASSED] DG1 B0
[06:47:15] [PASSED] ALDERLAKE_S A0
[06:47:15] [PASSED] ALDERLAKE_S B0
[06:47:15] [PASSED] ALDERLAKE_S C0
[06:47:15] [PASSED] ALDERLAKE_S D0
[06:47:15] [PASSED] ALDERLAKE_P A0
[06:47:15] [PASSED] ALDERLAKE_P B0
[06:47:15] [PASSED] ALDERLAKE_P C0
[06:47:15] [PASSED] ALDERLAKE_S RPLS D0
[06:47:15] [PASSED] ALDERLAKE_P RPLU E0
[06:47:15] [PASSED] DG2 G10 C0
[06:47:15] [PASSED] DG2 G11 B1
[06:47:15] [PASSED] DG2 G12 A1
[06:47:15] [PASSED] METEORLAKE 12.70(Xe_LPG) A0 13.00(Xe_LPM+) A0
[06:47:15] [PASSED] METEORLAKE 12.71(Xe_LPG) A0 13.00(Xe_LPM+) A0
[06:47:15] [PASSED] METEORLAKE 12.74(Xe_LPG+) A0 13.00(Xe_LPM+) A0
[06:47:15] [PASSED] LUNARLAKE 20.04(Xe2_LPG) A0 20.00(Xe2_LPM) A0
[06:47:15] [PASSED] LUNARLAKE 20.04(Xe2_LPG) B0 20.00(Xe2_LPM) A0
[06:47:15] [PASSED] BATTLEMAGE 20.01(Xe2_HPG) A0 13.01(Xe2_HPM) A1
[06:47:15] [PASSED] PANTHERLAKE 30.00(Xe3_LPG) A0 30.00(Xe3_LPM) A0
[06:47:15] ==================== [PASSED] xe_wa_gt =====================
[06:47:15] ====================== [PASSED] xe_wa ======================
[06:47:15] ============================================================
[06:47:15] Testing complete. Ran 597 tests: passed: 579, skipped: 18
[06:47:15] Elapsed time: 35.572s total, 4.195s configuring, 30.759s building, 0.605s running

+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/tests/.kunitconfig
[06:47:15] Configuring KUnit Kernel ...
Regenerating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[06:47:17] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[06:47:40] Starting KUnit Kernel (1/1)...
[06:47:40] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[06:47:41] ============ drm_test_pick_cmdline (2 subtests) ============
[06:47:41] [PASSED] drm_test_pick_cmdline_res_1920_1080_60
[06:47:41] =============== drm_test_pick_cmdline_named  ===============
[06:47:41] [PASSED] NTSC
[06:47:41] [PASSED] NTSC-J
[06:47:41] [PASSED] PAL
[06:47:41] [PASSED] PAL-M
[06:47:41] =========== [PASSED] drm_test_pick_cmdline_named ===========
[06:47:41] ============== [PASSED] drm_test_pick_cmdline ==============
[06:47:41] == drm_test_atomic_get_connector_for_encoder (1 subtest) ===
[06:47:41] [PASSED] drm_test_drm_atomic_get_connector_for_encoder
[06:47:41] ==== [PASSED] drm_test_atomic_get_connector_for_encoder ====
[06:47:41] =========== drm_validate_clone_mode (2 subtests) ===========
[06:47:41] ============== drm_test_check_in_clone_mode  ===============
[06:47:41] [PASSED] in_clone_mode
[06:47:41] [PASSED] not_in_clone_mode
[06:47:41] ========== [PASSED] drm_test_check_in_clone_mode ===========
[06:47:41] =============== drm_test_check_valid_clones  ===============
[06:47:41] [PASSED] not_in_clone_mode
[06:47:41] [PASSED] valid_clone
[06:47:41] [PASSED] invalid_clone
[06:47:41] =========== [PASSED] drm_test_check_valid_clones ===========
[06:47:41] ============= [PASSED] drm_validate_clone_mode =============
[06:47:41] ============= drm_validate_modeset (1 subtest) =============
[06:47:41] [PASSED] drm_test_check_connector_changed_modeset
[06:47:41] ============== [PASSED] drm_validate_modeset ===============
[06:47:41] ====== drm_test_bridge_get_current_state (2 subtests) ======
[06:47:41] [PASSED] drm_test_drm_bridge_get_current_state_atomic
[06:47:41] [PASSED] drm_test_drm_bridge_get_current_state_legacy
[06:47:41] ======== [PASSED] drm_test_bridge_get_current_state ========
[06:47:41] ====== drm_test_bridge_helper_reset_crtc (3 subtests) ======
[06:47:41] [PASSED] drm_test_drm_bridge_helper_reset_crtc_atomic
[06:47:41] [PASSED] drm_test_drm_bridge_helper_reset_crtc_atomic_disabled
[06:47:41] [PASSED] drm_test_drm_bridge_helper_reset_crtc_legacy
[06:47:41] ======== [PASSED] drm_test_bridge_helper_reset_crtc ========
[06:47:41] ============== drm_bridge_alloc (2 subtests) ===============
[06:47:41] [PASSED] drm_test_drm_bridge_alloc_basic
[06:47:41] [PASSED] drm_test_drm_bridge_alloc_get_put
[06:47:41] ================ [PASSED] drm_bridge_alloc =================
[06:47:41] ============= drm_cmdline_parser (40 subtests) =============
[06:47:41] [PASSED] drm_test_cmdline_force_d_only
[06:47:41] [PASSED] drm_test_cmdline_force_D_only_dvi
[06:47:41] [PASSED] drm_test_cmdline_force_D_only_hdmi
[06:47:41] [PASSED] drm_test_cmdline_force_D_only_not_digital
[06:47:41] [PASSED] drm_test_cmdline_force_e_only
[06:47:41] [PASSED] drm_test_cmdline_res
[06:47:41] [PASSED] drm_test_cmdline_res_vesa
[06:47:41] [PASSED] drm_test_cmdline_res_vesa_rblank
[06:47:41] [PASSED] drm_test_cmdline_res_rblank
[06:47:41] [PASSED] drm_test_cmdline_res_bpp
[06:47:41] [PASSED] drm_test_cmdline_res_refresh
[06:47:41] [PASSED] drm_test_cmdline_res_bpp_refresh
[06:47:41] [PASSED] drm_test_cmdline_res_bpp_refresh_interlaced
[06:47:41] [PASSED] drm_test_cmdline_res_bpp_refresh_margins
[06:47:41] [PASSED] drm_test_cmdline_res_bpp_refresh_force_off
[06:47:41] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on
[06:47:41] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on_analog
[06:47:41] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on_digital
[06:47:41] [PASSED] drm_test_cmdline_res_bpp_refresh_interlaced_margins_force_on
[06:47:41] [PASSED] drm_test_cmdline_res_margins_force_on
[06:47:41] [PASSED] drm_test_cmdline_res_vesa_margins
[06:47:41] [PASSED] drm_test_cmdline_name
[06:47:41] [PASSED] drm_test_cmdline_name_bpp
[06:47:41] [PASSED] drm_test_cmdline_name_option
[06:47:41] [PASSED] drm_test_cmdline_name_bpp_option
[06:47:41] [PASSED] drm_test_cmdline_rotate_0
[06:47:41] [PASSED] drm_test_cmdline_rotate_90
[06:47:41] [PASSED] drm_test_cmdline_rotate_180
[06:47:41] [PASSED] drm_test_cmdline_rotate_270
[06:47:41] [PASSED] drm_test_cmdline_hmirror
[06:47:41] [PASSED] drm_test_cmdline_vmirror
[06:47:41] [PASSED] drm_test_cmdline_margin_options
[06:47:41] [PASSED] drm_test_cmdline_multiple_options
[06:47:41] [PASSED] drm_test_cmdline_bpp_extra_and_option
[06:47:41] [PASSED] drm_test_cmdline_extra_and_option
[06:47:41] [PASSED] drm_test_cmdline_freestanding_options
[06:47:41] [PASSED] drm_test_cmdline_freestanding_force_e_and_options
[06:47:41] [PASSED] drm_test_cmdline_panel_orientation
[06:47:41] ================ drm_test_cmdline_invalid  =================
[06:47:41] [PASSED] margin_only
[06:47:41] [PASSED] interlace_only
[06:47:41] [PASSED] res_missing_x
[06:47:41] [PASSED] res_missing_y
[06:47:41] [PASSED] res_bad_y
[06:47:41] [PASSED] res_missing_y_bpp
[06:47:41] [PASSED] res_bad_bpp
[06:47:41] [PASSED] res_bad_refresh
[06:47:41] [PASSED] res_bpp_refresh_force_on_off
[06:47:41] [PASSED] res_invalid_mode
[06:47:41] [PASSED] res_bpp_wrong_place_mode
[06:47:41] [PASSED] name_bpp_refresh
[06:47:41] [PASSED] name_refresh
[06:47:41] [PASSED] name_refresh_wrong_mode
[06:47:41] [PASSED] name_refresh_invalid_mode
[06:47:41] [PASSED] rotate_multiple
[06:47:41] [PASSED] rotate_invalid_val
[06:47:41] [PASSED] rotate_truncated
[06:47:41] [PASSED] invalid_option
[06:47:41] [PASSED] invalid_tv_option
[06:47:41] [PASSED] truncated_tv_option
[06:47:41] ============ [PASSED] drm_test_cmdline_invalid =============
[06:47:41] =============== drm_test_cmdline_tv_options  ===============
[06:47:41] [PASSED] NTSC
[06:47:41] [PASSED] NTSC_443
[06:47:41] [PASSED] NTSC_J
[06:47:41] [PASSED] PAL
[06:47:41] [PASSED] PAL_M
[06:47:41] [PASSED] PAL_N
[06:47:41] [PASSED] SECAM
[06:47:41] [PASSED] MONO_525
[06:47:41] [PASSED] MONO_625
[06:47:41] =========== [PASSED] drm_test_cmdline_tv_options ===========
[06:47:41] =============== [PASSED] drm_cmdline_parser ================
[06:47:41] ========== drmm_connector_hdmi_init (20 subtests) ==========
[06:47:41] [PASSED] drm_test_connector_hdmi_init_valid
[06:47:41] [PASSED] drm_test_connector_hdmi_init_bpc_8
[06:47:41] [PASSED] drm_test_connector_hdmi_init_bpc_10
[06:47:41] [PASSED] drm_test_connector_hdmi_init_bpc_12
[06:47:41] [PASSED] drm_test_connector_hdmi_init_bpc_invalid
[06:47:41] [PASSED] drm_test_connector_hdmi_init_bpc_null
[06:47:41] [PASSED] drm_test_connector_hdmi_init_formats_empty
[06:47:41] [PASSED] drm_test_connector_hdmi_init_formats_no_rgb
[06:47:41] === drm_test_connector_hdmi_init_formats_yuv420_allowed  ===
[06:47:41] [PASSED] supported_formats=0x9 yuv420_allowed=1
[06:47:41] [PASSED] supported_formats=0x9 yuv420_allowed=0
[06:47:41] [PASSED] supported_formats=0x5 yuv420_allowed=1
[06:47:41] [PASSED] supported_formats=0x5 yuv420_allowed=0
[06:47:41] === [PASSED] drm_test_connector_hdmi_init_formats_yuv420_allowed ===
[06:47:41] [PASSED] drm_test_connector_hdmi_init_null_ddc
[06:47:41] [PASSED] drm_test_connector_hdmi_init_null_product
[06:47:41] [PASSED] drm_test_connector_hdmi_init_null_vendor
[06:47:41] [PASSED] drm_test_connector_hdmi_init_product_length_exact
[06:47:41] [PASSED] drm_test_connector_hdmi_init_product_length_too_long
[06:47:41] [PASSED] drm_test_connector_hdmi_init_product_valid
[06:47:41] [PASSED] drm_test_connector_hdmi_init_vendor_length_exact
[06:47:41] [PASSED] drm_test_connector_hdmi_init_vendor_length_too_long
[06:47:41] [PASSED] drm_test_connector_hdmi_init_vendor_valid
[06:47:41] ========= drm_test_connector_hdmi_init_type_valid  =========
[06:47:41] [PASSED] HDMI-A
[06:47:41] [PASSED] HDMI-B
[06:47:41] ===== [PASSED] drm_test_connector_hdmi_init_type_valid =====
[06:47:41] ======== drm_test_connector_hdmi_init_type_invalid  ========
[06:47:41] [PASSED] Unknown
[06:47:41] [PASSED] VGA
[06:47:41] [PASSED] DVI-I
[06:47:41] [PASSED] DVI-D
[06:47:41] [PASSED] DVI-A
[06:47:41] [PASSED] Composite
[06:47:41] [PASSED] SVIDEO
[06:47:41] [PASSED] LVDS
[06:47:41] [PASSED] Component
[06:47:41] [PASSED] DIN
[06:47:41] [PASSED] DP
[06:47:41] [PASSED] TV
[06:47:41] [PASSED] eDP
[06:47:41] [PASSED] Virtual
[06:47:41] [PASSED] DSI
[06:47:41] [PASSED] DPI
[06:47:41] [PASSED] Writeback
[06:47:41] [PASSED] SPI
[06:47:41] [PASSED] USB
[06:47:41] ==== [PASSED] drm_test_connector_hdmi_init_type_invalid ====
[06:47:41] ============ [PASSED] drmm_connector_hdmi_init =============
[06:47:41] ============= drmm_connector_init (3 subtests) =============
[06:47:41] [PASSED] drm_test_drmm_connector_init
[06:47:41] [PASSED] drm_test_drmm_connector_init_null_ddc
[06:47:41] ========= drm_test_drmm_connector_init_type_valid  =========
[06:47:41] [PASSED] Unknown
[06:47:41] [PASSED] VGA
[06:47:41] [PASSED] DVI-I
[06:47:41] [PASSED] DVI-D
[06:47:41] [PASSED] DVI-A
[06:47:41] [PASSED] Composite
[06:47:41] [PASSED] SVIDEO
[06:47:41] [PASSED] LVDS
[06:47:41] [PASSED] Component
[06:47:41] [PASSED] DIN
[06:47:41] [PASSED] DP
[06:47:41] [PASSED] HDMI-A
[06:47:41] [PASSED] HDMI-B
[06:47:41] [PASSED] TV
[06:47:41] [PASSED] eDP
[06:47:41] [PASSED] Virtual
[06:47:41] [PASSED] DSI
[06:47:41] [PASSED] DPI
[06:47:41] [PASSED] Writeback
[06:47:41] [PASSED] SPI
[06:47:41] [PASSED] USB
[06:47:41] ===== [PASSED] drm_test_drmm_connector_init_type_valid =====
[06:47:41] =============== [PASSED] drmm_connector_init ===============
[06:47:41] ========= drm_connector_dynamic_init (6 subtests) ==========
[06:47:41] [PASSED] drm_test_drm_connector_dynamic_init
[06:47:41] [PASSED] drm_test_drm_connector_dynamic_init_null_ddc
[06:47:41] [PASSED] drm_test_drm_connector_dynamic_init_not_added
[06:47:41] [PASSED] drm_test_drm_connector_dynamic_init_properties
[06:47:41] ===== drm_test_drm_connector_dynamic_init_type_valid  ======
[06:47:41] [PASSED] Unknown
[06:47:41] [PASSED] VGA
[06:47:41] [PASSED] DVI-I
[06:47:41] [PASSED] DVI-D
[06:47:41] [PASSED] DVI-A
[06:47:41] [PASSED] Composite
[06:47:41] [PASSED] SVIDEO
[06:47:41] [PASSED] LVDS
[06:47:41] [PASSED] Component
[06:47:41] [PASSED] DIN
[06:47:41] [PASSED] DP
[06:47:41] [PASSED] HDMI-A
[06:47:41] [PASSED] HDMI-B
[06:47:41] [PASSED] TV
[06:47:41] [PASSED] eDP
[06:47:41] [PASSED] Virtual
[06:47:41] [PASSED] DSI
[06:47:41] [PASSED] DPI
[06:47:41] [PASSED] Writeback
[06:47:41] [PASSED] SPI
[06:47:41] [PASSED] USB
[06:47:41] = [PASSED] drm_test_drm_connector_dynamic_init_type_valid ==
[06:47:41] ======== drm_test_drm_connector_dynamic_init_name  =========
[06:47:41] [PASSED] Unknown
[06:47:41] [PASSED] VGA
[06:47:41] [PASSED] DVI-I
[06:47:41] [PASSED] DVI-D
[06:47:41] [PASSED] DVI-A
[06:47:41] [PASSED] Composite
[06:47:41] [PASSED] SVIDEO
[06:47:41] [PASSED] LVDS
[06:47:41] [PASSED] Component
[06:47:41] [PASSED] DIN
[06:47:41] [PASSED] DP
[06:47:41] [PASSED] HDMI-A
[06:47:41] [PASSED] HDMI-B
[06:47:41] [PASSED] TV
[06:47:41] [PASSED] eDP
[06:47:41] [PASSED] Virtual
[06:47:41] [PASSED] DSI
[06:47:41] [PASSED] DPI
[06:47:41] [PASSED] Writeback
[06:47:41] [PASSED] SPI
[06:47:41] [PASSED] USB
[06:47:41] ==== [PASSED] drm_test_drm_connector_dynamic_init_name =====
[06:47:41] =========== [PASSED] drm_connector_dynamic_init ============
[06:47:41] ==== drm_connector_dynamic_register_early (4 subtests) =====
[06:47:41] [PASSED] drm_test_drm_connector_dynamic_register_early_on_list
[06:47:41] [PASSED] drm_test_drm_connector_dynamic_register_early_defer
[06:47:41] [PASSED] drm_test_drm_connector_dynamic_register_early_no_init
[06:47:41] [PASSED] drm_test_drm_connector_dynamic_register_early_no_mode_object
[06:47:41] ====== [PASSED] drm_connector_dynamic_register_early =======
[06:47:41] ======= drm_connector_dynamic_register (7 subtests) ========
[06:47:41] [PASSED] drm_test_drm_connector_dynamic_register_on_list
[06:47:41] [PASSED] drm_test_drm_connector_dynamic_register_no_defer
[06:47:41] [PASSED] drm_test_drm_connector_dynamic_register_no_init
[06:47:41] [PASSED] drm_test_drm_connector_dynamic_register_mode_object
[06:47:41] [PASSED] drm_test_drm_connector_dynamic_register_sysfs
[06:47:41] [PASSED] drm_test_drm_connector_dynamic_register_sysfs_name
[06:47:41] [PASSED] drm_test_drm_connector_dynamic_register_debugfs
[06:47:41] ========= [PASSED] drm_connector_dynamic_register ==========
[06:47:41] = drm_connector_attach_broadcast_rgb_property (2 subtests) =
[06:47:41] [PASSED] drm_test_drm_connector_attach_broadcast_rgb_property
[06:47:41] [PASSED] drm_test_drm_connector_attach_broadcast_rgb_property_hdmi_connector
[06:47:41] === [PASSED] drm_connector_attach_broadcast_rgb_property ===
[06:47:41] ========== drm_get_tv_mode_from_name (2 subtests) ==========
[06:47:41] ========== drm_test_get_tv_mode_from_name_valid  ===========
[06:47:41] [PASSED] NTSC
[06:47:41] [PASSED] NTSC-443
[06:47:41] [PASSED] NTSC-J
[06:47:41] [PASSED] PAL
[06:47:41] [PASSED] PAL-M
[06:47:41] [PASSED] PAL-N
[06:47:41] [PASSED] SECAM
[06:47:41] [PASSED] Mono
[06:47:41] ====== [PASSED] drm_test_get_tv_mode_from_name_valid =======
[06:47:41] [PASSED] drm_test_get_tv_mode_from_name_truncated
[06:47:41] ============ [PASSED] drm_get_tv_mode_from_name ============
[06:47:41] = drm_test_connector_hdmi_compute_mode_clock (12 subtests) =
[06:47:41] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb
[06:47:41] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_10bpc
[06:47:41] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_10bpc_vic_1
[06:47:41] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_12bpc
[06:47:41] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_12bpc_vic_1
[06:47:41] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_double
[06:47:41] = drm_test_connector_hdmi_compute_mode_clock_yuv420_valid  =
[06:47:41] [PASSED] VIC 96
[06:47:41] [PASSED] VIC 97
[06:47:41] [PASSED] VIC 101
[06:47:41] [PASSED] VIC 102
[06:47:41] [PASSED] VIC 106
[06:47:41] [PASSED] VIC 107
[06:47:41] === [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_valid ===
[06:47:41] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_10_bpc
[06:47:41] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_12_bpc
[06:47:41] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_8_bpc
[06:47:41] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_10_bpc
[06:47:41] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_12_bpc
[06:47:41] === [PASSED] drm_test_connector_hdmi_compute_mode_clock ====
[06:47:41] == drm_hdmi_connector_get_broadcast_rgb_name (2 subtests) ==
[06:47:41] === drm_test_drm_hdmi_connector_get_broadcast_rgb_name  ====
[06:47:41] [PASSED] Automatic
[06:47:41] [PASSED] Full
[06:47:41] [PASSED] Limited 16:235
[06:47:41] === [PASSED] drm_test_drm_hdmi_connector_get_broadcast_rgb_name ===
[06:47:41] [PASSED] drm_test_drm_hdmi_connector_get_broadcast_rgb_name_invalid
[06:47:41] ==== [PASSED] drm_hdmi_connector_get_broadcast_rgb_name ====
[06:47:41] == drm_hdmi_connector_get_output_format_name (2 subtests) ==
[06:47:41] === drm_test_drm_hdmi_connector_get_output_format_name  ====
[06:47:41] [PASSED] RGB
[06:47:41] [PASSED] YUV 4:2:0
[06:47:41] [PASSED] YUV 4:2:2
[06:47:41] [PASSED] YUV 4:4:4
[06:47:41] === [PASSED] drm_test_drm_hdmi_connector_get_output_format_name ===
[06:47:41] [PASSED] drm_test_drm_hdmi_connector_get_output_format_name_invalid
[06:47:41] ==== [PASSED] drm_hdmi_connector_get_output_format_name ====
[06:47:41] ============= drm_damage_helper (21 subtests) ==============
[06:47:41] [PASSED] drm_test_damage_iter_no_damage
[06:47:41] [PASSED] drm_test_damage_iter_no_damage_fractional_src
[06:47:41] [PASSED] drm_test_damage_iter_no_damage_src_moved
[06:47:41] [PASSED] drm_test_damage_iter_no_damage_fractional_src_moved
[06:47:41] [PASSED] drm_test_damage_iter_no_damage_not_visible
[06:47:41] [PASSED] drm_test_damage_iter_no_damage_no_crtc
[06:47:41] [PASSED] drm_test_damage_iter_no_damage_no_fb
[06:47:41] [PASSED] drm_test_damage_iter_simple_damage
[06:47:41] [PASSED] drm_test_damage_iter_single_damage
[06:47:41] [PASSED] drm_test_damage_iter_single_damage_intersect_src
[06:47:41] [PASSED] drm_test_damage_iter_single_damage_outside_src
[06:47:41] [PASSED] drm_test_damage_iter_single_damage_fractional_src
[06:47:41] [PASSED] drm_test_damage_iter_single_damage_intersect_fractional_src
[06:47:41] [PASSED] drm_test_damage_iter_single_damage_outside_fractional_src
[06:47:41] [PASSED] drm_test_damage_iter_single_damage_src_moved
[06:47:41] [PASSED] drm_test_damage_iter_single_damage_fractional_src_moved
[06:47:41] [PASSED] drm_test_damage_iter_damage
[06:47:41] [PASSED] drm_test_damage_iter_damage_one_intersect
[06:47:41] [PASSED] drm_test_damage_iter_damage_one_outside
[06:47:41] [PASSED] drm_test_damage_iter_damage_src_moved
[06:47:41] [PASSED] drm_test_damage_iter_damage_not_visible
[06:47:41] ================ [PASSED] drm_damage_helper ================
[06:47:41] ============== drm_dp_mst_helper (3 subtests) ==============
[06:47:41] ============== drm_test_dp_mst_calc_pbn_mode  ==============
[06:47:41] [PASSED] Clock 154000 BPP 30 DSC disabled
[06:47:41] [PASSED] Clock 234000 BPP 30 DSC disabled
[06:47:41] [PASSED] Clock 297000 BPP 24 DSC disabled
[06:47:41] [PASSED] Clock 332880 BPP 24 DSC enabled
[06:47:41] [PASSED] Clock 324540 BPP 24 DSC enabled
[06:47:41] ========== [PASSED] drm_test_dp_mst_calc_pbn_mode ==========
[06:47:41] ============== drm_test_dp_mst_calc_pbn_div  ===============
[06:47:41] [PASSED] Link rate 2000000 lane count 4
[06:47:41] [PASSED] Link rate 2000000 lane count 2
[06:47:41] [PASSED] Link rate 2000000 lane count 1
[06:47:41] [PASSED] Link rate 1350000 lane count 4
[06:47:41] [PASSED] Link rate 1350000 lane count 2
[06:47:41] [PASSED] Link rate 1350000 lane count 1
[06:47:41] [PASSED] Link rate 1000000 lane count 4
[06:47:41] [PASSED] Link rate 1000000 lane count 2
[06:47:41] [PASSED] Link rate 1000000 lane count 1
[06:47:41] [PASSED] Link rate 810000 lane count 4
[06:47:41] [PASSED] Link rate 810000 lane count 2
[06:47:41] [PASSED] Link rate 810000 lane count 1
[06:47:41] [PASSED] Link rate 540000 lane count 4
[06:47:41] [PASSED] Link rate 540000 lane count 2
[06:47:41] [PASSED] Link rate 540000 lane count 1
[06:47:41] [PASSED] Link rate 270000 lane count 4
[06:47:41] [PASSED] Link rate 270000 lane count 2
[06:47:41] [PASSED] Link rate 270000 lane count 1
[06:47:41] [PASSED] Link rate 162000 lane count 4
[06:47:41] [PASSED] Link rate 162000 lane count 2
[06:47:41] [PASSED] Link rate 162000 lane count 1
[06:47:41] ========== [PASSED] drm_test_dp_mst_calc_pbn_div ===========
[06:47:41] ========= drm_test_dp_mst_sideband_msg_req_decode  =========
[06:47:41] [PASSED] DP_ENUM_PATH_RESOURCES with port number
[06:47:41] [PASSED] DP_POWER_UP_PHY with port number
[06:47:41] [PASSED] DP_POWER_DOWN_PHY with port number
[06:47:41] [PASSED] DP_ALLOCATE_PAYLOAD with SDP stream sinks
[06:47:41] [PASSED] DP_ALLOCATE_PAYLOAD with port number
[06:47:41] [PASSED] DP_ALLOCATE_PAYLOAD with VCPI
[06:47:41] [PASSED] DP_ALLOCATE_PAYLOAD with PBN
[06:47:41] [PASSED] DP_QUERY_PAYLOAD with port number
[06:47:41] [PASSED] DP_QUERY_PAYLOAD with VCPI
[06:47:41] [PASSED] DP_REMOTE_DPCD_READ with port number
[06:47:41] [PASSED] DP_REMOTE_DPCD_READ with DPCD address
[06:47:41] [PASSED] DP_REMOTE_DPCD_READ with max number of bytes
[06:47:41] [PASSED] DP_REMOTE_DPCD_WRITE with port number
[06:47:41] [PASSED] DP_REMOTE_DPCD_WRITE with DPCD address
[06:47:41] [PASSED] DP_REMOTE_DPCD_WRITE with data array
[06:47:41] [PASSED] DP_REMOTE_I2C_READ with port number
[06:47:41] [PASSED] DP_REMOTE_I2C_READ with I2C device ID
[06:47:41] [PASSED] DP_REMOTE_I2C_READ with transactions array
[06:47:41] [PASSED] DP_REMOTE_I2C_WRITE with port number
[06:47:41] [PASSED] DP_REMOTE_I2C_WRITE with I2C device ID
[06:47:41] [PASSED] DP_REMOTE_I2C_WRITE with data array
[06:47:41] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream ID
[06:47:41] [PASSED] DP_QUERY_STREAM_ENC_STATUS with client ID
[06:47:41] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream event
[06:47:41] [PASSED] DP_QUERY_STREAM_ENC_STATUS with valid stream event
[06:47:41] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream behavior
[06:47:41] [PASSED] DP_QUERY_STREAM_ENC_STATUS with a valid stream behavior
[06:47:41] ===== [PASSED] drm_test_dp_mst_sideband_msg_req_decode =====
[06:47:41] ================ [PASSED] drm_dp_mst_helper ================
[06:47:41] ================== drm_exec (7 subtests) ===================
[06:47:41] [PASSED] sanitycheck
[06:47:41] [PASSED] test_lock
[06:47:41] [PASSED] test_lock_unlock
[06:47:41] [PASSED] test_duplicates
[06:47:41] [PASSED] test_prepare
[06:47:41] [PASSED] test_prepare_array
[06:47:41] [PASSED] test_multiple_loops
[06:47:41] ==================== [PASSED] drm_exec =====================
[06:47:41] =========== drm_format_helper_test (17 subtests) ===========
[06:47:41] ============== drm_test_fb_xrgb8888_to_gray8  ==============
[06:47:41] [PASSED] single_pixel_source_buffer
[06:47:41] [PASSED] single_pixel_clip_rectangle
[06:47:41] [PASSED] well_known_colors
[06:47:41] [PASSED] destination_pitch
[06:47:41] ========== [PASSED] drm_test_fb_xrgb8888_to_gray8 ==========
[06:47:41] ============= drm_test_fb_xrgb8888_to_rgb332  ==============
[06:47:41] [PASSED] single_pixel_source_buffer
[06:47:41] [PASSED] single_pixel_clip_rectangle
[06:47:41] [PASSED] well_known_colors
[06:47:41] [PASSED] destination_pitch
[06:47:41] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb332 ==========
[06:47:41] ============= drm_test_fb_xrgb8888_to_rgb565  ==============
[06:47:41] [PASSED] single_pixel_source_buffer
[06:47:41] [PASSED] single_pixel_clip_rectangle
[06:47:41] [PASSED] well_known_colors
[06:47:41] [PASSED] destination_pitch
[06:47:41] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb565 ==========
[06:47:41] ============ drm_test_fb_xrgb8888_to_xrgb1555  =============
[06:47:41] [PASSED] single_pixel_source_buffer
[06:47:41] [PASSED] single_pixel_clip_rectangle
[06:47:41] [PASSED] well_known_colors
[06:47:41] [PASSED] destination_pitch
[06:47:41] ======== [PASSED] drm_test_fb_xrgb8888_to_xrgb1555 =========
[06:47:41] ============ drm_test_fb_xrgb8888_to_argb1555  =============
[06:47:41] [PASSED] single_pixel_source_buffer
[06:47:41] [PASSED] single_pixel_clip_rectangle
[06:47:41] [PASSED] well_known_colors
[06:47:41] [PASSED] destination_pitch
[06:47:41] ======== [PASSED] drm_test_fb_xrgb8888_to_argb1555 =========
[06:47:41] ============ drm_test_fb_xrgb8888_to_rgba5551  =============
[06:47:41] [PASSED] single_pixel_source_buffer
[06:47:41] [PASSED] single_pixel_clip_rectangle
[06:47:41] [PASSED] well_known_colors
[06:47:41] [PASSED] destination_pitch
[06:47:41] ======== [PASSED] drm_test_fb_xrgb8888_to_rgba5551 =========
[06:47:41] ============= drm_test_fb_xrgb8888_to_rgb888  ==============
[06:47:41] [PASSED] single_pixel_source_buffer
[06:47:41] [PASSED] single_pixel_clip_rectangle
[06:47:41] [PASSED] well_known_colors
[06:47:41] [PASSED] destination_pitch
[06:47:41] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb888 ==========
[06:47:41] ============= drm_test_fb_xrgb8888_to_bgr888  ==============
[06:47:41] [PASSED] single_pixel_source_buffer
[06:47:41] [PASSED] single_pixel_clip_rectangle
[06:47:41] [PASSED] well_known_colors
[06:47:41] [PASSED] destination_pitch
[06:47:41] ========= [PASSED] drm_test_fb_xrgb8888_to_bgr888 ==========
[06:47:41] ============ drm_test_fb_xrgb8888_to_argb8888  =============
[06:47:41] [PASSED] single_pixel_source_buffer
[06:47:41] [PASSED] single_pixel_clip_rectangle
[06:47:41] [PASSED] well_known_colors
[06:47:41] [PASSED] destination_pitch
[06:47:41] ======== [PASSED] drm_test_fb_xrgb8888_to_argb8888 =========
[06:47:41] =========== drm_test_fb_xrgb8888_to_xrgb2101010  ===========
[06:47:41] [PASSED] single_pixel_source_buffer
[06:47:41] [PASSED] single_pixel_clip_rectangle
[06:47:41] [PASSED] well_known_colors
[06:47:41] [PASSED] destination_pitch
[06:47:41] ======= [PASSED] drm_test_fb_xrgb8888_to_xrgb2101010 =======
[06:47:41] =========== drm_test_fb_xrgb8888_to_argb2101010  ===========
[06:47:41] [PASSED] single_pixel_source_buffer
[06:47:41] [PASSED] single_pixel_clip_rectangle
[06:47:41] [PASSED] well_known_colors
[06:47:41] [PASSED] destination_pitch
[06:47:41] ======= [PASSED] drm_test_fb_xrgb8888_to_argb2101010 =======
[06:47:41] ============== drm_test_fb_xrgb8888_to_mono  ===============
[06:47:41] [PASSED] single_pixel_source_buffer
[06:47:41] [PASSED] single_pixel_clip_rectangle
[06:47:41] [PASSED] well_known_colors
[06:47:41] [PASSED] destination_pitch
[06:47:41] ========== [PASSED] drm_test_fb_xrgb8888_to_mono ===========
[06:47:41] ==================== drm_test_fb_swab  =====================
[06:47:41] [PASSED] single_pixel_source_buffer
[06:47:41] [PASSED] single_pixel_clip_rectangle
[06:47:41] [PASSED] well_known_colors
[06:47:41] [PASSED] destination_pitch
[06:47:41] ================ [PASSED] drm_test_fb_swab =================
[06:47:41] ============ drm_test_fb_xrgb8888_to_xbgr8888  =============
[06:47:41] [PASSED] single_pixel_source_buffer
[06:47:41] [PASSED] single_pixel_clip_rectangle
[06:47:41] [PASSED] well_known_colors
[06:47:41] [PASSED] destination_pitch
[06:47:41] ======== [PASSED] drm_test_fb_xrgb8888_to_xbgr8888 =========
[06:47:41] ============ drm_test_fb_xrgb8888_to_abgr8888  =============
[06:47:41] [PASSED] single_pixel_source_buffer
[06:47:41] [PASSED] single_pixel_clip_rectangle
[06:47:41] [PASSED] well_known_colors
[06:47:41] [PASSED] destination_pitch
[06:47:41] ======== [PASSED] drm_test_fb_xrgb8888_to_abgr8888 =========
[06:47:41] ================= drm_test_fb_clip_offset  =================
[06:47:41] [PASSED] pass through
[06:47:41] [PASSED] horizontal offset
[06:47:41] [PASSED] vertical offset
[06:47:41] [PASSED] horizontal and vertical offset
[06:47:41] [PASSED] horizontal offset (custom pitch)
[06:47:41] [PASSED] vertical offset (custom pitch)
[06:47:41] [PASSED] horizontal and vertical offset (custom pitch)
[06:47:41] ============= [PASSED] drm_test_fb_clip_offset =============
[06:47:41] =================== drm_test_fb_memcpy  ====================
[06:47:41] [PASSED] single_pixel_source_buffer: XR24 little-endian (0x34325258)
[06:47:41] [PASSED] single_pixel_source_buffer: XRA8 little-endian (0x38415258)
[06:47:41] [PASSED] single_pixel_source_buffer: YU24 little-endian (0x34325559)
[06:47:41] [PASSED] single_pixel_clip_rectangle: XB24 little-endian (0x34324258)
[06:47:41] [PASSED] single_pixel_clip_rectangle: XRA8 little-endian (0x38415258)
[06:47:41] [PASSED] single_pixel_clip_rectangle: YU24 little-endian (0x34325559)
[06:47:41] [PASSED] well_known_colors: XB24 little-endian (0x34324258)
[06:47:41] [PASSED] well_known_colors: XRA8 little-endian (0x38415258)
[06:47:41] [PASSED] well_known_colors: YU24 little-endian (0x34325559)
[06:47:41] [PASSED] destination_pitch: XB24 little-endian (0x34324258)
[06:47:41] [PASSED] destination_pitch: XRA8 little-endian (0x38415258)
[06:47:41] [PASSED] destination_pitch: YU24 little-endian (0x34325559)
[06:47:41] =============== [PASSED] drm_test_fb_memcpy ================
[06:47:41] ============= [PASSED] drm_format_helper_test ==============
[06:47:41] ================= drm_format (18 subtests) =================
[06:47:41] [PASSED] drm_test_format_block_width_invalid
[06:47:41] [PASSED] drm_test_format_block_width_one_plane
[06:47:41] [PASSED] drm_test_format_block_width_two_plane
[06:47:41] [PASSED] drm_test_format_block_width_three_plane
[06:47:41] [PASSED] drm_test_format_block_width_tiled
[06:47:41] [PASSED] drm_test_format_block_height_invalid
[06:47:41] [PASSED] drm_test_format_block_height_one_plane
[06:47:41] [PASSED] drm_test_format_block_height_two_plane
[06:47:41] [PASSED] drm_test_format_block_height_three_plane
[06:47:41] [PASSED] drm_test_format_block_height_tiled
[06:47:41] [PASSED] drm_test_format_min_pitch_invalid
[06:47:41] [PASSED] drm_test_format_min_pitch_one_plane_8bpp
[06:47:41] [PASSED] drm_test_format_min_pitch_one_plane_16bpp
[06:47:41] [PASSED] drm_test_format_min_pitch_one_plane_24bpp
[06:47:41] [PASSED] drm_test_format_min_pitch_one_plane_32bpp
[06:47:41] [PASSED] drm_test_format_min_pitch_two_plane
[06:47:41] [PASSED] drm_test_format_min_pitch_three_plane_8bpp
[06:47:41] [PASSED] drm_test_format_min_pitch_tiled
[06:47:41] =================== [PASSED] drm_format ====================
[06:47:41] ============== drm_framebuffer (10 subtests) ===============
[06:47:41] ========== drm_test_framebuffer_check_src_coords  ==========
[06:47:41] [PASSED] Success: source fits into fb
[06:47:41] [PASSED] Fail: overflowing fb with x-axis coordinate
[06:47:41] [PASSED] Fail: overflowing fb with y-axis coordinate
[06:47:41] [PASSED] Fail: overflowing fb with source width
[06:47:41] [PASSED] Fail: overflowing fb with source height
[06:47:41] ====== [PASSED] drm_test_framebuffer_check_src_coords ======
[06:47:41] [PASSED] drm_test_framebuffer_cleanup
[06:47:41] =============== drm_test_framebuffer_create  ===============
[06:47:41] [PASSED] ABGR8888 normal sizes
[06:47:41] [PASSED] ABGR8888 max sizes
[06:47:41] [PASSED] ABGR8888 pitch greater than min required
[06:47:41] [PASSED] ABGR8888 pitch less than min required
[06:47:41] [PASSED] ABGR8888 Invalid width
[06:47:41] [PASSED] ABGR8888 Invalid buffer handle
[06:47:41] [PASSED] No pixel format
[06:47:41] [PASSED] ABGR8888 Width 0
[06:47:41] [PASSED] ABGR8888 Height 0
[06:47:41] [PASSED] ABGR8888 Out of bound height * pitch combination
[06:47:41] [PASSED] ABGR8888 Large buffer offset
[06:47:41] [PASSED] ABGR8888 Buffer offset for inexistent plane
[06:47:41] [PASSED] ABGR8888 Invalid flag
[06:47:41] [PASSED] ABGR8888 Set DRM_MODE_FB_MODIFIERS without modifiers
[06:47:41] [PASSED] ABGR8888 Valid buffer modifier
[06:47:41] [PASSED] ABGR8888 Invalid buffer modifier(DRM_FORMAT_MOD_SAMSUNG_64_32_TILE)
[06:47:41] [PASSED] ABGR8888 Extra pitches without DRM_MODE_FB_MODIFIERS
[06:47:41] [PASSED] ABGR8888 Extra pitches with DRM_MODE_FB_MODIFIERS
[06:47:41] [PASSED] NV12 Normal sizes
[06:47:41] [PASSED] NV12 Max sizes
[06:47:41] [PASSED] NV12 Invalid pitch
[06:47:41] [PASSED] NV12 Invalid modifier/missing DRM_MODE_FB_MODIFIERS flag
[06:47:41] [PASSED] NV12 different  modifier per-plane
[06:47:41] [PASSED] NV12 with DRM_FORMAT_MOD_SAMSUNG_64_32_TILE
[06:47:41] [PASSED] NV12 Valid modifiers without DRM_MODE_FB_MODIFIERS
[06:47:41] [PASSED] NV12 Modifier for inexistent plane
[06:47:41] [PASSED] NV12 Handle for inexistent plane
[06:47:41] [PASSED] NV12 Handle for inexistent plane without DRM_MODE_FB_MODIFIERS
[06:47:41] [PASSED] YVU420 DRM_MODE_FB_MODIFIERS set without modifier
[06:47:41] [PASSED] YVU420 Normal sizes
[06:47:41] [PASSED] YVU420 Max sizes
[06:47:41] [PASSED] YVU420 Invalid pitch
[06:47:41] [PASSED] YVU420 Different pitches
[06:47:41] [PASSED] YVU420 Different buffer offsets/pitches
[06:47:41] [PASSED] YVU420 Modifier set just for plane 0, without DRM_MODE_FB_MODIFIERS
[06:47:41] [PASSED] YVU420 Modifier set just for planes 0, 1, without DRM_MODE_FB_MODIFIERS
[06:47:41] [PASSED] YVU420 Modifier set just for plane 0, 1, with DRM_MODE_FB_MODIFIERS
[06:47:41] [PASSED] YVU420 Valid modifier
[06:47:41] [PASSED] YVU420 Different modifiers per plane
[06:47:41] [PASSED] YVU420 Modifier for inexistent plane
[06:47:41] [PASSED] YUV420_10BIT Invalid modifier(DRM_FORMAT_MOD_LINEAR)
[06:47:41] [PASSED] X0L2 Normal sizes
[06:47:41] [PASSED] X0L2 Max sizes
[06:47:41] [PASSED] X0L2 Invalid pitch
[06:47:41] [PASSED] X0L2 Pitch greater than minimum required
[06:47:41] [PASSED] X0L2 Handle for inexistent plane
[06:47:41] [PASSED] X0L2 Offset for inexistent plane, without DRM_MODE_FB_MODIFIERS set
[06:47:41] [PASSED] X0L2 Modifier without DRM_MODE_FB_MODIFIERS set
[06:47:41] [PASSED] X0L2 Valid modifier
[06:47:41] [PASSED] X0L2 Modifier for inexistent plane
[06:47:41] =========== [PASSED] drm_test_framebuffer_create ===========
[06:47:41] [PASSED] drm_test_framebuffer_free
[06:47:41] [PASSED] drm_test_framebuffer_init
[06:47:41] [PASSED] drm_test_framebuffer_init_bad_format
[06:47:41] [PASSED] drm_test_framebuffer_init_dev_mismatch
[06:47:41] [PASSED] drm_test_framebuffer_lookup
[06:47:41] [PASSED] drm_test_framebuffer_lookup_inexistent
[06:47:41] [PASSED] drm_test_framebuffer_modifiers_not_supported
[06:47:41] ================= [PASSED] drm_framebuffer =================
[06:47:41] ================ drm_gem_shmem (8 subtests) ================
[06:47:41] [PASSED] drm_gem_shmem_test_obj_create
[06:47:41] [PASSED] drm_gem_shmem_test_obj_create_private
[06:47:41] [PASSED] drm_gem_shmem_test_pin_pages
[06:47:41] [PASSED] drm_gem_shmem_test_vmap
[06:47:41] [PASSED] drm_gem_shmem_test_get_sg_table
[06:47:41] [PASSED] drm_gem_shmem_test_get_pages_sgt
[06:47:41] [PASSED] drm_gem_shmem_test_madvise
[06:47:41] [PASSED] drm_gem_shmem_test_purge
[06:47:41] ================== [PASSED] drm_gem_shmem ==================
[06:47:41] === drm_atomic_helper_connector_hdmi_check (27 subtests) ===
[06:47:41] [PASSED] drm_test_check_broadcast_rgb_auto_cea_mode
[06:47:41] [PASSED] drm_test_check_broadcast_rgb_auto_cea_mode_vic_1
[06:47:41] [PASSED] drm_test_check_broadcast_rgb_full_cea_mode
[06:47:41] [PASSED] drm_test_check_broadcast_rgb_full_cea_mode_vic_1
[06:47:41] [PASSED] drm_test_check_broadcast_rgb_limited_cea_mode
[06:47:41] [PASSED] drm_test_check_broadcast_rgb_limited_cea_mode_vic_1
[06:47:41] ====== drm_test_check_broadcast_rgb_cea_mode_yuv420  =======
[06:47:41] [PASSED] Automatic
[06:47:41] [PASSED] Full
[06:47:41] [PASSED] Limited 16:235
[06:47:41] == [PASSED] drm_test_check_broadcast_rgb_cea_mode_yuv420 ===
[06:47:41] [PASSED] drm_test_check_broadcast_rgb_crtc_mode_changed
[06:47:41] [PASSED] drm_test_check_broadcast_rgb_crtc_mode_not_changed
[06:47:41] [PASSED] drm_test_check_disable_connector
[06:47:41] [PASSED] drm_test_check_hdmi_funcs_reject_rate
[06:47:41] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_rgb
[06:47:41] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_yuv420
[06:47:41] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_ignore_yuv422
[06:47:41] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_ignore_yuv420
[06:47:41] [PASSED] drm_test_check_driver_unsupported_fallback_yuv420
[06:47:41] [PASSED] drm_test_check_output_bpc_crtc_mode_changed
[06:47:41] [PASSED] drm_test_check_output_bpc_crtc_mode_not_changed
[06:47:41] [PASSED] drm_test_check_output_bpc_dvi
[06:47:41] [PASSED] drm_test_check_output_bpc_format_vic_1
[06:47:41] [PASSED] drm_test_check_output_bpc_format_display_8bpc_only
[06:47:41] [PASSED] drm_test_check_output_bpc_format_display_rgb_only
[06:47:41] [PASSED] drm_test_check_output_bpc_format_driver_8bpc_only
[06:47:41] [PASSED] drm_test_check_output_bpc_format_driver_rgb_only
[06:47:41] [PASSED] drm_test_check_tmds_char_rate_rgb_8bpc
[06:47:41] [PASSED] drm_test_check_tmds_char_rate_rgb_10bpc
[06:47:41] [PASSED] drm_test_check_tmds_char_rate_rgb_12bpc
[06:47:41] ===== [PASSED] drm_atomic_helper_connector_hdmi_check ======
[06:47:41] === drm_atomic_helper_connector_hdmi_reset (6 subtests) ====
[06:47:41] [PASSED] drm_test_check_broadcast_rgb_value
[06:47:41] [PASSED] drm_test_check_bpc_8_value
[06:47:41] [PASSED] drm_test_check_bpc_10_value
[06:47:41] [PASSED] drm_test_check_bpc_12_value
[06:47:41] [PASSED] drm_test_check_format_value
[06:47:41] [PASSED] drm_test_check_tmds_char_value
[06:47:41] ===== [PASSED] drm_atomic_helper_connector_hdmi_reset ======
[06:47:41] = drm_atomic_helper_connector_hdmi_mode_valid (4 subtests) =
[06:47:41] [PASSED] drm_test_check_mode_valid
[06:47:41] [PASSED] drm_test_check_mode_valid_reject
[06:47:41] [PASSED] drm_test_check_mode_valid_reject_rate
[06:47:41] [PASSED] drm_test_check_mode_valid_reject_max_clock
[06:47:41] === [PASSED] drm_atomic_helper_connector_hdmi_mode_valid ===
[06:47:41] = drm_atomic_helper_connector_hdmi_infoframes (5 subtests) =
[06:47:41] [PASSED] drm_test_check_infoframes
[06:47:41] [PASSED] drm_test_check_reject_avi_infoframe
[06:47:41] [PASSED] drm_test_check_reject_hdr_infoframe_bpc_8
[06:47:41] [PASSED] drm_test_check_reject_hdr_infoframe_bpc_10
[06:47:41] [PASSED] drm_test_check_reject_audio_infoframe
[06:47:41] === [PASSED] drm_atomic_helper_connector_hdmi_infoframes ===
[06:47:41] ================= drm_managed (2 subtests) =================
[06:47:41] [PASSED] drm_test_managed_release_action
[06:47:41] [PASSED] drm_test_managed_run_action
[06:47:41] =================== [PASSED] drm_managed ===================
[06:47:41] =================== drm_mm (6 subtests) ====================
[06:47:41] [PASSED] drm_test_mm_init
[06:47:41] [PASSED] drm_test_mm_debug
[06:47:41] [PASSED] drm_test_mm_align32
[06:47:41] [PASSED] drm_test_mm_align64
[06:47:41] [PASSED] drm_test_mm_lowest
[06:47:41] [PASSED] drm_test_mm_highest
[06:47:41] ===================== [PASSED] drm_mm ======================
[06:47:41] ============= drm_modes_analog_tv (5 subtests) =============
[06:47:41] [PASSED] drm_test_modes_analog_tv_mono_576i
[06:47:41] [PASSED] drm_test_modes_analog_tv_ntsc_480i
[06:47:41] [PASSED] drm_test_modes_analog_tv_ntsc_480i_inlined
[06:47:41] [PASSED] drm_test_modes_analog_tv_pal_576i
[06:47:41] [PASSED] drm_test_modes_analog_tv_pal_576i_inlined
[06:47:41] =============== [PASSED] drm_modes_analog_tv ===============
[06:47:41] ============== drm_plane_helper (2 subtests) ===============
[06:47:41] =============== drm_test_check_plane_state  ================
[06:47:41] [PASSED] clipping_simple
[06:47:41] [PASSED] clipping_rotate_reflect
[06:47:41] [PASSED] positioning_simple
[06:47:41] [PASSED] upscaling
[06:47:41] [PASSED] downscaling
[06:47:41] [PASSED] rounding1
[06:47:41] [PASSED] rounding2
[06:47:41] [PASSED] rounding3
[06:47:41] [PASSED] rounding4
[06:47:41] =========== [PASSED] drm_test_check_plane_state ============
[06:47:41] =========== drm_test_check_invalid_plane_state  ============
[06:47:41] [PASSED] positioning_invalid
[06:47:41] [PASSED] upscaling_invalid
[06:47:41] [PASSED] downscaling_invalid
[06:47:41] ======= [PASSED] drm_test_check_invalid_plane_state ========
[06:47:41] ================ [PASSED] drm_plane_helper =================
[06:47:41] ====== drm_connector_helper_tv_get_modes (1 subtest) =======
[06:47:41] ====== drm_test_connector_helper_tv_get_modes_check  =======
[06:47:41] [PASSED] None
[06:47:41] [PASSED] PAL
[06:47:41] [PASSED] NTSC
[06:47:41] [PASSED] Both, NTSC Default
[06:47:41] [PASSED] Both, PAL Default
[06:47:41] [PASSED] Both, NTSC Default, with PAL on command-line
[06:47:41] [PASSED] Both, PAL Default, with NTSC on command-line
[06:47:41] == [PASSED] drm_test_connector_helper_tv_get_modes_check ===
[06:47:41] ======== [PASSED] drm_connector_helper_tv_get_modes ========
[06:47:41] ================== drm_rect (9 subtests) ===================
[06:47:41] [PASSED] drm_test_rect_clip_scaled_div_by_zero
[06:47:41] [PASSED] drm_test_rect_clip_scaled_not_clipped
[06:47:41] [PASSED] drm_test_rect_clip_scaled_clipped
[06:47:41] [PASSED] drm_test_rect_clip_scaled_signed_vs_unsigned
[06:47:41] ================= drm_test_rect_intersect  =================
[06:47:41] [PASSED] top-left x bottom-right: 2x2+1+1 x 2x2+0+0
[06:47:41] [PASSED] top-right x bottom-left: 2x2+0+0 x 2x2+1-1
[06:47:41] [PASSED] bottom-left x top-right: 2x2+1-1 x 2x2+0+0
[06:47:41] [PASSED] bottom-right x top-left: 2x2+0+0 x 2x2+1+1
[06:47:41] [PASSED] right x left: 2x1+0+0 x 3x1+1+0
[06:47:41] [PASSED] left x right: 3x1+1+0 x 2x1+0+0
[06:47:41] [PASSED] up x bottom: 1x2+0+0 x 1x3+0-1
[06:47:41] [PASSED] bottom x up: 1x3+0-1 x 1x2+0+0
[06:47:41] [PASSED] touching corner: 1x1+0+0 x 2x2+1+1
[06:47:41] [PASSED] touching side: 1x1+0+0 x 1x1+1+0
[06:47:41] [PASSED] equal rects: 2x2+0+0 x 2x2+0+0
[06:47:41] [PASSED] inside another: 2x2+0+0 x 1x1+1+1
[06:47:41] [PASSED] far away: 1x1+0+0 x 1x1+3+6
[06:47:41] [PASSED] points intersecting: 0x0+5+10 x 0x0+5+10
[06:47:41] [PASSED] points not intersecting: 0x0+0+0 x 0x0+5+10
[06:47:41] ============= [PASSED] drm_test_rect_intersect =============
[06:47:41] ================ drm_test_rect_calc_hscale  ================
[06:47:41] [PASSED] normal use
[06:47:41] [PASSED] out of max range
[06:47:41] [PASSED] out of min range
[06:47:41] [PASSED] zero dst
[06:47:41] [PASSED] negative src
[06:47:41] [PASSED] negative dst
[06:47:41] ============ [PASSED] drm_test_rect_calc_hscale ============
[06:47:41] ================ drm_test_rect_calc_vscale  ================
[06:47:41] [PASSED] normal use
[06:47:41] [PASSED] out of max range
[06:47:41] [PASSED] out of min range
[06:47:41] [PASSED] zero dst
[06:47:41] [PASSED] negative src
[06:47:41] [PASSED] negative dst
stty: 'standard input': Inappropriate ioctl for device
[06:47:41] ============ [PASSED] drm_test_rect_calc_vscale ============
[06:47:41] ================== drm_test_rect_rotate  ===================
[06:47:41] [PASSED] reflect-x
[06:47:41] [PASSED] reflect-y
[06:47:41] [PASSED] rotate-0
[06:47:41] [PASSED] rotate-90
[06:47:41] [PASSED] rotate-180
[06:47:41] [PASSED] rotate-270
[06:47:41] ============== [PASSED] drm_test_rect_rotate ===============
[06:47:41] ================ drm_test_rect_rotate_inv  =================
[06:47:41] [PASSED] reflect-x
[06:47:41] [PASSED] reflect-y
[06:47:41] [PASSED] rotate-0
[06:47:41] [PASSED] rotate-90
[06:47:41] [PASSED] rotate-180
[06:47:41] [PASSED] rotate-270
[06:47:41] ============ [PASSED] drm_test_rect_rotate_inv =============
[06:47:41] ==================== [PASSED] drm_rect =====================
[06:47:41] ============ drm_sysfb_modeset_test (1 subtest) ============
[06:47:41] ============ drm_test_sysfb_build_fourcc_list  =============
[06:47:41] [PASSED] no native formats
[06:47:41] [PASSED] XRGB8888 as native format
[06:47:41] [PASSED] remove duplicates
[06:47:41] [PASSED] convert alpha formats
[06:47:41] [PASSED] random formats
[06:47:41] ======== [PASSED] drm_test_sysfb_build_fourcc_list =========
[06:47:41] ============= [PASSED] drm_sysfb_modeset_test ==============
[06:47:41] ================== drm_fixp (2 subtests) ===================
[06:47:41] [PASSED] drm_test_int2fixp
[06:47:41] [PASSED] drm_test_sm2fixp
[06:47:41] ==================== [PASSED] drm_fixp =====================
[06:47:41] ============================================================
[06:47:41] Testing complete. Ran 621 tests: passed: 621
[06:47:41] Elapsed time: 25.703s total, 1.739s configuring, 23.793s building, 0.139s running

+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/ttm/tests/.kunitconfig
[06:47:41] Configuring KUnit Kernel ...
Regenerating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[06:47:42] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[06:47:52] Starting KUnit Kernel (1/1)...
[06:47:52] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[06:47:52] ================= ttm_device (5 subtests) ==================
[06:47:52] [PASSED] ttm_device_init_basic
[06:47:52] [PASSED] ttm_device_init_multiple
[06:47:52] [PASSED] ttm_device_fini_basic
[06:47:52] [PASSED] ttm_device_init_no_vma_man
[06:47:52] ================== ttm_device_init_pools  ==================
[06:47:52] [PASSED] No DMA allocations, no DMA32 required
[06:47:52] [PASSED] DMA allocations, DMA32 required
[06:47:52] [PASSED] No DMA allocations, DMA32 required
[06:47:52] [PASSED] DMA allocations, no DMA32 required
[06:47:52] ============== [PASSED] ttm_device_init_pools ==============
[06:47:52] =================== [PASSED] ttm_device ====================
[06:47:52] ================== ttm_pool (8 subtests) ===================
[06:47:52] ================== ttm_pool_alloc_basic  ===================
[06:47:52] [PASSED] One page
[06:47:52] [PASSED] More than one page
[06:47:52] [PASSED] Above the allocation limit
[06:47:52] [PASSED] One page, with coherent DMA mappings enabled
[06:47:52] [PASSED] Above the allocation limit, with coherent DMA mappings enabled
[06:47:52] ============== [PASSED] ttm_pool_alloc_basic ===============
[06:47:52] ============== ttm_pool_alloc_basic_dma_addr  ==============
[06:47:52] [PASSED] One page
[06:47:52] [PASSED] More than one page
[06:47:52] [PASSED] Above the allocation limit
[06:47:52] [PASSED] One page, with coherent DMA mappings enabled
[06:47:52] [PASSED] Above the allocation limit, with coherent DMA mappings enabled
[06:47:52] ========== [PASSED] ttm_pool_alloc_basic_dma_addr ==========
[06:47:52] [PASSED] ttm_pool_alloc_order_caching_match
[06:47:52] [PASSED] ttm_pool_alloc_caching_mismatch
[06:47:52] [PASSED] ttm_pool_alloc_order_mismatch
[06:47:52] [PASSED] ttm_pool_free_dma_alloc
[06:47:52] [PASSED] ttm_pool_free_no_dma_alloc
[06:47:52] [PASSED] ttm_pool_fini_basic
[06:47:52] ==================== [PASSED] ttm_pool =====================
[06:47:52] ================ ttm_resource (8 subtests) =================
[06:47:52] ================= ttm_resource_init_basic  =================
[06:47:52] [PASSED] Init resource in TTM_PL_SYSTEM
[06:47:52] [PASSED] Init resource in TTM_PL_VRAM
[06:47:52] [PASSED] Init resource in a private placement
[06:47:52] [PASSED] Init resource in TTM_PL_SYSTEM, set placement flags
[06:47:52] ============= [PASSED] ttm_resource_init_basic =============
[06:47:52] [PASSED] ttm_resource_init_pinned
[06:47:52] [PASSED] ttm_resource_fini_basic
[06:47:52] [PASSED] ttm_resource_manager_init_basic
[06:47:52] [PASSED] ttm_resource_manager_usage_basic
[06:47:52] [PASSED] ttm_resource_manager_set_used_basic
[06:47:52] [PASSED] ttm_sys_man_alloc_basic
[06:47:52] [PASSED] ttm_sys_man_free_basic
[06:47:52] ================== [PASSED] ttm_resource ===================
[06:47:52] =================== ttm_tt (15 subtests) ===================
[06:47:52] ==================== ttm_tt_init_basic  ====================
[06:47:52] [PASSED] Page-aligned size
[06:47:52] [PASSED] Extra pages requested
[06:47:52] ================ [PASSED] ttm_tt_init_basic ================
[06:47:52] [PASSED] ttm_tt_init_misaligned
[06:47:52] [PASSED] ttm_tt_fini_basic
[06:47:52] [PASSED] ttm_tt_fini_sg
[06:47:52] [PASSED] ttm_tt_fini_shmem
[06:47:52] [PASSED] ttm_tt_create_basic
[06:47:52] [PASSED] ttm_tt_create_invalid_bo_type
[06:47:52] [PASSED] ttm_tt_create_ttm_exists
[06:47:52] [PASSED] ttm_tt_create_failed
[06:47:52] [PASSED] ttm_tt_destroy_basic
[06:47:52] [PASSED] ttm_tt_populate_null_ttm
[06:47:52] [PASSED] ttm_tt_populate_populated_ttm
[06:47:52] [PASSED] ttm_tt_unpopulate_basic
[06:47:52] [PASSED] ttm_tt_unpopulate_empty_ttm
[06:47:52] [PASSED] ttm_tt_swapin_basic
[06:47:52] ===================== [PASSED] ttm_tt ======================
[06:47:52] =================== ttm_bo (14 subtests) ===================
[06:47:52] =========== ttm_bo_reserve_optimistic_no_ticket  ===========
[06:47:52] [PASSED] Cannot be interrupted and sleeps
[06:47:52] [PASSED] Cannot be interrupted, locks straight away
[06:47:52] [PASSED] Can be interrupted, sleeps
[06:47:52] ======= [PASSED] ttm_bo_reserve_optimistic_no_ticket =======
[06:47:52] [PASSED] ttm_bo_reserve_locked_no_sleep
[06:47:52] [PASSED] ttm_bo_reserve_no_wait_ticket
[06:47:52] [PASSED] ttm_bo_reserve_double_resv
[06:47:52] [PASSED] ttm_bo_reserve_interrupted
[06:47:52] [PASSED] ttm_bo_reserve_deadlock
[06:47:52] [PASSED] ttm_bo_unreserve_basic
[06:47:52] [PASSED] ttm_bo_unreserve_pinned
[06:47:52] [PASSED] ttm_bo_unreserve_bulk
[06:47:52] [PASSED] ttm_bo_fini_basic
[06:47:52] [PASSED] ttm_bo_fini_shared_resv
[06:47:52] [PASSED] ttm_bo_pin_basic
[06:47:52] [PASSED] ttm_bo_pin_unpin_resource
[06:47:52] [PASSED] ttm_bo_multiple_pin_one_unpin
[06:47:52] ===================== [PASSED] ttm_bo ======================
[06:47:52] ============== ttm_bo_validate (22 subtests) ===============
[06:47:52] ============== ttm_bo_init_reserved_sys_man  ===============
[06:47:52] [PASSED] Buffer object for userspace
[06:47:52] [PASSED] Kernel buffer object
[06:47:52] [PASSED] Shared buffer object
[06:47:52] ========== [PASSED] ttm_bo_init_reserved_sys_man ===========
[06:47:52] ============== ttm_bo_init_reserved_mock_man  ==============
[06:47:52] [PASSED] Buffer object for userspace
[06:47:52] [PASSED] Kernel buffer object
[06:47:52] [PASSED] Shared buffer object
[06:47:52] ========== [PASSED] ttm_bo_init_reserved_mock_man ==========
[06:47:52] [PASSED] ttm_bo_init_reserved_resv
[06:47:52] ================== ttm_bo_validate_basic  ==================
[06:47:52] [PASSED] Buffer object for userspace
[06:47:52] [PASSED] Kernel buffer object
[06:47:52] [PASSED] Shared buffer object
[06:47:52] ============== [PASSED] ttm_bo_validate_basic ==============
[06:47:52] [PASSED] ttm_bo_validate_invalid_placement
[06:47:52] ============= ttm_bo_validate_same_placement  ==============
[06:47:52] [PASSED] System manager
[06:47:52] [PASSED] VRAM manager
[06:47:52] ========= [PASSED] ttm_bo_validate_same_placement ==========
[06:47:52] [PASSED] ttm_bo_validate_failed_alloc
[06:47:52] [PASSED] ttm_bo_validate_pinned
[06:47:52] [PASSED] ttm_bo_validate_busy_placement
[06:47:52] ================ ttm_bo_validate_multihop  =================
[06:47:52] [PASSED] Buffer object for userspace
[06:47:52] [PASSED] Kernel buffer object
[06:47:52] [PASSED] Shared buffer object
[06:47:52] ============ [PASSED] ttm_bo_validate_multihop =============
[06:47:52] ========== ttm_bo_validate_no_placement_signaled  ==========
[06:47:52] [PASSED] Buffer object in system domain, no page vector
[06:47:52] [PASSED] Buffer object in system domain with an existing page vector
[06:47:52] ====== [PASSED] ttm_bo_validate_no_placement_signaled ======
[06:47:52] ======== ttm_bo_validate_no_placement_not_signaled  ========
[06:47:52] [PASSED] Buffer object for userspace
[06:47:52] [PASSED] Kernel buffer object
[06:47:52] [PASSED] Shared buffer object
[06:47:52] ==== [PASSED] ttm_bo_validate_no_placement_not_signaled ====
[06:47:52] [PASSED] ttm_bo_validate_move_fence_signaled
[06:47:52] ========= ttm_bo_validate_move_fence_not_signaled  =========
[06:47:52] [PASSED] Waits for GPU
[06:47:52] [PASSED] Tries to lock straight away
[06:47:52] ===== [PASSED] ttm_bo_validate_move_fence_not_signaled =====
[06:47:52] [PASSED] ttm_bo_validate_swapout
[06:47:52] [PASSED] ttm_bo_validate_happy_evict
[06:47:52] [PASSED] ttm_bo_validate_all_pinned_evict
[06:47:52] [PASSED] ttm_bo_validate_allowed_only_evict
[06:47:52] [PASSED] ttm_bo_validate_deleted_evict
[06:47:52] [PASSED] ttm_bo_validate_busy_domain_evict
[06:47:52] [PASSED] ttm_bo_validate_evict_gutting
[06:47:52] [PASSED] ttm_bo_validate_recrusive_evict
stty: 'standard input': Inappropriate ioctl for device
[06:47:52] ================= [PASSED] ttm_bo_validate =================
[06:47:52] ============================================================
[06:47:52] Testing complete. Ran 102 tests: passed: 102
[06:47:52] Elapsed time: 11.335s total, 1.715s configuring, 9.405s building, 0.184s running

+ cleanup
++ stat -c %u:%g /kernel
+ chown -R 1003:1003 /kernel



^ permalink raw reply	[flat|nested] 7+ messages in thread

* ✓ Xe.CI.BAT: success for drm/xe: Set GT rp min frequency as 1.2GHz default for BMG/CRI (rev4)
  2026-03-26  6:34 [PATCH v4 0/1] drm/xe: Set GT rp min frequency as 1.2GHz default for BMG/CRI Nareshkumar Gollakoti
  2026-03-26  6:34 ` [PATCH v4 1/1] " Nareshkumar Gollakoti
  2026-03-26  6:47 ` ✓ CI.KUnit: success for drm/xe: Set GT rp min frequency as 1.2GHz default for BMG/CRI (rev4) Patchwork
@ 2026-03-26  7:30 ` Patchwork
  2026-03-26 18:25 ` ✓ Xe.CI.FULL: " Patchwork
  3 siblings, 0 replies; 7+ messages in thread
From: Patchwork @ 2026-03-26  7:30 UTC (permalink / raw)
  To: Nareshkumar Gollakoti; +Cc: intel-xe

[-- Attachment #1: Type: text/plain, Size: 1429 bytes --]

== Series Details ==

Series: drm/xe: Set GT rp min frequency as 1.2GHz default for BMG/CRI (rev4)
URL   : https://patchwork.freedesktop.org/series/161656/
State : success

== Summary ==

CI Bug Log - changes from xe-4788-817e894dd8588c9eee61b1fbd743859ddba35f78_BAT -> xe-pw-161656v4_BAT
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  

Participating hosts (14 -> 14)
------------------------------

  No changes in participating hosts

Known issues
------------

  Here are the changes found in xe-pw-161656v4_BAT that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@xe_waitfence@engine:
    - bat-dg2-oem2:       [PASS][1] -> [FAIL][2] ([Intel XE#6519])
   [1]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4788-817e894dd8588c9eee61b1fbd743859ddba35f78/bat-dg2-oem2/igt@xe_waitfence@engine.html
   [2]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161656v4/bat-dg2-oem2/igt@xe_waitfence@engine.html

  
  [Intel XE#6519]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6519


Build changes
-------------

  * Linux: xe-4788-817e894dd8588c9eee61b1fbd743859ddba35f78 -> xe-pw-161656v4

  IGT_8831: 8831
  xe-4788-817e894dd8588c9eee61b1fbd743859ddba35f78: 817e894dd8588c9eee61b1fbd743859ddba35f78
  xe-pw-161656v4: 161656v4

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161656v4/index.html

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^ permalink raw reply	[flat|nested] 7+ messages in thread

* ✓ Xe.CI.FULL: success for drm/xe: Set GT rp min frequency as 1.2GHz default for BMG/CRI (rev4)
  2026-03-26  6:34 [PATCH v4 0/1] drm/xe: Set GT rp min frequency as 1.2GHz default for BMG/CRI Nareshkumar Gollakoti
                   ` (2 preceding siblings ...)
  2026-03-26  7:30 ` ✓ Xe.CI.BAT: " Patchwork
@ 2026-03-26 18:25 ` Patchwork
  2026-03-31 21:16   ` Matt Roper
  3 siblings, 1 reply; 7+ messages in thread
From: Patchwork @ 2026-03-26 18:25 UTC (permalink / raw)
  To: Nareshkumar Gollakoti; +Cc: intel-xe

[-- Attachment #1: Type: text/plain, Size: 2016 bytes --]

== Series Details ==

Series: drm/xe: Set GT rp min frequency as 1.2GHz default for BMG/CRI (rev4)
URL   : https://patchwork.freedesktop.org/series/161656/
State : success

== Summary ==

CI Bug Log - changes from xe-4788-817e894dd8588c9eee61b1fbd743859ddba35f78_FULL -> xe-pw-161656v4_FULL
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  

Participating hosts (2 -> 2)
------------------------------

  No changes in participating hosts

Known issues
------------

  Here are the changes found in xe-pw-161656v4_FULL that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@kms_vrr@seamless-rr-switch-virtual@pipe-a-edp-1:
    - shard-lnl:          [PASS][1] -> [FAIL][2] ([Intel XE#2142]) +1 other test fail
   [1]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4788-817e894dd8588c9eee61b1fbd743859ddba35f78/shard-lnl-2/igt@kms_vrr@seamless-rr-switch-virtual@pipe-a-edp-1.html
   [2]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161656v4/shard-lnl-5/igt@kms_vrr@seamless-rr-switch-virtual@pipe-a-edp-1.html

  
#### Possible fixes ####

  * igt@kms_vrr@cmrr@pipe-a-edp-1:
    - shard-lnl:          [FAIL][3] ([Intel XE#4459]) -> [PASS][4] +1 other test pass
   [3]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4788-817e894dd8588c9eee61b1fbd743859ddba35f78/shard-lnl-6/igt@kms_vrr@cmrr@pipe-a-edp-1.html
   [4]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161656v4/shard-lnl-8/igt@kms_vrr@cmrr@pipe-a-edp-1.html

  
  [Intel XE#2142]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2142
  [Intel XE#4459]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4459


Build changes
-------------

  * Linux: xe-4788-817e894dd8588c9eee61b1fbd743859ddba35f78 -> xe-pw-161656v4

  IGT_8831: 8831
  xe-4788-817e894dd8588c9eee61b1fbd743859ddba35f78: 817e894dd8588c9eee61b1fbd743859ddba35f78
  xe-pw-161656v4: 161656v4

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161656v4/index.html

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^ permalink raw reply	[flat|nested] 7+ messages in thread

* Re: ✓ Xe.CI.FULL: success for drm/xe: Set GT rp min frequency as 1.2GHz default for BMG/CRI (rev4)
  2026-03-26 18:25 ` ✓ Xe.CI.FULL: " Patchwork
@ 2026-03-31 21:16   ` Matt Roper
  0 siblings, 0 replies; 7+ messages in thread
From: Matt Roper @ 2026-03-31 21:16 UTC (permalink / raw)
  To: intel-xe; +Cc: Nareshkumar Gollakoti

On Thu, Mar 26, 2026 at 06:25:06PM -0000, Patchwork wrote:
> == Series Details ==
> 
> Series: drm/xe: Set GT rp min frequency as 1.2GHz default for BMG/CRI (rev4)
> URL   : https://patchwork.freedesktop.org/series/161656/
> State : success
> 
> == Summary ==
> 
> CI Bug Log - changes from xe-4788-817e894dd8588c9eee61b1fbd743859ddba35f78_FULL -> xe-pw-161656v4_FULL
> ====================================================
> 
> Summary
> -------
> 
>   **SUCCESS**
> 
>   No regressions found.
> 

Applied to drm-xe-next.  Thanks for the patch and review.


Matt

>   
> 
> Participating hosts (2 -> 2)
> ------------------------------
> 
>   No changes in participating hosts
> 
> Known issues
> ------------
> 
>   Here are the changes found in xe-pw-161656v4_FULL that come from known issues:
> 
> ### IGT changes ###
> 
> #### Issues hit ####
> 
>   * igt@kms_vrr@seamless-rr-switch-virtual@pipe-a-edp-1:
>     - shard-lnl:          [PASS][1] -> [FAIL][2] ([Intel XE#2142]) +1 other test fail
>    [1]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4788-817e894dd8588c9eee61b1fbd743859ddba35f78/shard-lnl-2/igt@kms_vrr@seamless-rr-switch-virtual@pipe-a-edp-1.html
>    [2]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161656v4/shard-lnl-5/igt@kms_vrr@seamless-rr-switch-virtual@pipe-a-edp-1.html
> 
>   
> #### Possible fixes ####
> 
>   * igt@kms_vrr@cmrr@pipe-a-edp-1:
>     - shard-lnl:          [FAIL][3] ([Intel XE#4459]) -> [PASS][4] +1 other test pass
>    [3]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4788-817e894dd8588c9eee61b1fbd743859ddba35f78/shard-lnl-6/igt@kms_vrr@cmrr@pipe-a-edp-1.html
>    [4]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161656v4/shard-lnl-8/igt@kms_vrr@cmrr@pipe-a-edp-1.html
> 
>   
>   [Intel XE#2142]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2142
>   [Intel XE#4459]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4459
> 
> 
> Build changes
> -------------
> 
>   * Linux: xe-4788-817e894dd8588c9eee61b1fbd743859ddba35f78 -> xe-pw-161656v4
> 
>   IGT_8831: 8831
>   xe-4788-817e894dd8588c9eee61b1fbd743859ddba35f78: 817e894dd8588c9eee61b1fbd743859ddba35f78
>   xe-pw-161656v4: 161656v4
> 
> == Logs ==
> 
> For more details see: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161656v4/index.html

-- 
Matt Roper
Graphics Software Engineer
Linux GPU Platform Enablement
Intel Corporation

^ permalink raw reply	[flat|nested] 7+ messages in thread

end of thread, other threads:[~2026-03-31 21:16 UTC | newest]

Thread overview: 7+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2026-03-26  6:34 [PATCH v4 0/1] drm/xe: Set GT rp min frequency as 1.2GHz default for BMG/CRI Nareshkumar Gollakoti
2026-03-26  6:34 ` [PATCH v4 1/1] " Nareshkumar Gollakoti
2026-03-30 18:29   ` Belgaumkar, Vinay
2026-03-26  6:47 ` ✓ CI.KUnit: success for drm/xe: Set GT rp min frequency as 1.2GHz default for BMG/CRI (rev4) Patchwork
2026-03-26  7:30 ` ✓ Xe.CI.BAT: " Patchwork
2026-03-26 18:25 ` ✓ Xe.CI.FULL: " Patchwork
2026-03-31 21:16   ` Matt Roper

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