[PATCH] drm/xe: Add Wa_14026626235

[Nitin Gote <nitin.r.gote@intel.com>]

Wa_14026626235 requires two changes for graphics version 35.10:

1. Clear bit 6 (9th on state change mode) of PSS_CHICKEN (0x7044) via
   an LRC workaround applied per render context.

2. Disable preemption for the render engine by setting the GuC
   preemption timeout to 0. This prevents the HW from halting in the
   middle of a 3DPRIMITIVE command and inserting a flush.

Cc: Matt Roper <matthew.d.roper@intel.com>
Cc: Tejas Upadhyay <tejas.upadhyay@intel.com>
Signed-off-by: Nitin Gote <nitin.r.gote@intel.com>
---
 drivers/gpu/drm/xe/regs/xe_gt_regs.h | 1 +
 drivers/gpu/drm/xe/xe_guc_submit.c   | 8 ++++++++
 drivers/gpu/drm/xe/xe_wa.c           | 4 ++++
 drivers/gpu/drm/xe/xe_wa_oob.rules   | 1 +
 4 files changed, 14 insertions(+)

diff --git a/drivers/gpu/drm/xe/regs/xe_gt_regs.h b/drivers/gpu/drm/xe/regs/xe_gt_regs.h
index 4ebaa0888a43..db45d7908ebb 100644
--- a/drivers/gpu/drm/xe/regs/xe_gt_regs.h
+++ b/drivers/gpu/drm/xe/regs/xe_gt_regs.h
@@ -167,6 +167,7 @@
 
 #define XEHP_PSS_CHICKEN			XE_REG_MCR(0x7044, XE_REG_OPTION_MASKED)
 #define   FLSH_IGNORES_PSD			REG_BIT(10)
+#define   PSS_CHICKEN_9TH_ON_STATE_CHANGE	REG_BIT(6)
 #define   FD_END_COLLECT			REG_BIT(5)
 
 #define SC_INSTDONE				XE_REG(0x7100)
diff --git a/drivers/gpu/drm/xe/xe_guc_submit.c b/drivers/gpu/drm/xe/xe_guc_submit.c
index a145234f662b..d2bb574d422b 100644
--- a/drivers/gpu/drm/xe/xe_guc_submit.c
+++ b/drivers/gpu/drm/xe/xe_guc_submit.c
@@ -12,6 +12,8 @@
 
 #include <drm/drm_managed.h>
 
+#include <generated/xe_wa_oob.h>
+
 #include "abi/guc_actions_abi.h"
 #include "abi/guc_actions_slpc_abi.h"
 #include "abi/guc_klvs_abi.h"
@@ -44,6 +46,7 @@
 #include "xe_trace.h"
 #include "xe_uc_fw.h"
 #include "xe_vm.h"
+#include "xe_wa.h"
 
 #define XE_GUC_EXEC_QUEUE_CGP_CONTEXT_ERROR_LEN		6
 
@@ -531,6 +534,11 @@ static void init_policies(struct xe_guc *guc, struct xe_exec_queue *q)
 	xe_gt_assert(guc_to_gt(guc), exec_queue_registered(q) &&
 		     !xe_exec_queue_is_multi_queue_secondary(q));
 
+	/* Wa_14026626235: Disable preemption for render engine */
+	if (q->class == XE_ENGINE_CLASS_RENDER &&
+	    XE_GT_WA(q->gt, 14026626235))
+		preempt_timeout_us = 0;
+
 	if (q->flags & EXEC_QUEUE_FLAG_LOW_LATENCY)
 		slpc_exec_queue_freq_req |= SLPC_CTX_FREQ_REQ_IS_COMPUTE;
 
diff --git a/drivers/gpu/drm/xe/xe_wa.c b/drivers/gpu/drm/xe/xe_wa.c
index 546296f0220b..fe9ca153b33d 100644
--- a/drivers/gpu/drm/xe/xe_wa.c
+++ b/drivers/gpu/drm/xe/xe_wa.c
@@ -789,6 +789,10 @@ static const struct xe_rtp_entry_sr lrc_was[] = {
 		       ENGINE_CLASS(RENDER)),
 	  XE_RTP_ACTIONS(SET(CHICKEN_RASTER_1, DIS_CLIP_NEGATIVE_BOUNDING_BOX))
 	},
+	{ XE_RTP_NAME("14026626235"),
+	  XE_RTP_RULES(GRAPHICS_VERSION(3510), ENGINE_CLASS(RENDER)),
+	  XE_RTP_ACTIONS(CLR(XEHP_PSS_CHICKEN, PSS_CHICKEN_9TH_ON_STATE_CHANGE))
+	},
 };
 
 static __maybe_unused const struct xe_rtp_entry oob_was[] = {
diff --git a/drivers/gpu/drm/xe/xe_wa_oob.rules b/drivers/gpu/drm/xe/xe_wa_oob.rules
index 80b54b195f20..3f2582568171 100644
--- a/drivers/gpu/drm/xe/xe_wa_oob.rules
+++ b/drivers/gpu/drm/xe/xe_wa_oob.rules
@@ -58,3 +58,4 @@
 
 14025883347	MEDIA_VERSION_RANGE(1301, 3503)
 		GRAPHICS_VERSION_RANGE(2004, 3005)
+14026626235	GRAPHICS_VERSION(3510)
-- 
2.50.1