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d="scan'208";a="228232891" Received: from dut-2a59.iind.intel.com ([10.190.239.113]) by fmviesa004.fm.intel.com with ESMTP; 01 Apr 2026 02:03:32 -0700 From: Chaitanya Kumar Borah To: intel-xe@lists.freedesktop.org, intel-gfx@lists.freedesktop.org Cc: uma.shankar@intel.com, chaitanya.kumar.borah@intel.com, pranay.samala@intel.com Subject: [PATCH 2/3] drm/i915: Fix color blob reference handling in intel_plane_state Date: Wed, 1 Apr 2026 14:08:40 +0530 Message-Id: <20260401083841.4081587-2-chaitanya.kumar.borah@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20260401083841.4081587-1-chaitanya.kumar.borah@intel.com> References: <20260401083841.4081587-1-chaitanya.kumar.borah@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-BeenThere: intel-xe@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel Xe graphics driver List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-xe-bounces@lists.freedesktop.org Sender: "Intel-xe" Take proper references for hw color blobs (degamma_lut, gamma_lut, ctm, lut_3d) in intel_plane_duplicate_state() and drop them in intel_plane_destroy_state(). v2: - handle blobs in hw state clear/copy Fixes: 3b7476e786c2 ("drm/i915/color: Add framework to program PRE/POST CSC LUT") Fixes: a78f1b6baf4d ("drm/i915/color: Add framework to program CSC") Fixes: 65db7a1f9cf7 ("drm/i915/color: Add 3D LUT to color pipeline") Reviewed-by: Pranay Samala #v1 Signed-off-by: Chaitanya Kumar Borah --- drivers/gpu/drm/i915/display/intel_plane.c | 36 ++++++++++++++++++++++ 1 file changed, 36 insertions(+) diff --git a/drivers/gpu/drm/i915/display/intel_plane.c b/drivers/gpu/drm/i915/display/intel_plane.c index 82f445c83158..23988121065d 100644 --- a/drivers/gpu/drm/i915/display/intel_plane.c +++ b/drivers/gpu/drm/i915/display/intel_plane.c @@ -144,6 +144,15 @@ intel_plane_duplicate_state(struct drm_plane *plane) if (intel_state->hw.fb) drm_framebuffer_get(intel_state->hw.fb); + if (intel_state->hw.degamma_lut) + drm_property_blob_get(intel_state->hw.degamma_lut); + if (intel_state->hw.gamma_lut) + drm_property_blob_get(intel_state->hw.gamma_lut); + if (intel_state->hw.ctm) + drm_property_blob_get(intel_state->hw.ctm); + if (intel_state->hw.lut_3d) + drm_property_blob_get(intel_state->hw.lut_3d); + return &intel_state->uapi; } @@ -167,6 +176,16 @@ intel_plane_destroy_state(struct drm_plane *plane, __drm_atomic_helper_plane_destroy_state(&plane_state->uapi); if (plane_state->hw.fb) drm_framebuffer_put(plane_state->hw.fb); + + if (plane_state->hw.degamma_lut) + drm_property_blob_put(plane_state->hw.degamma_lut); + if (plane_state->hw.gamma_lut) + drm_property_blob_put(plane_state->hw.gamma_lut); + if (plane_state->hw.ctm) + drm_property_blob_put(plane_state->hw.ctm); + if (plane_state->hw.lut_3d) + drm_property_blob_put(plane_state->hw.lut_3d); + kfree(plane_state); } @@ -317,6 +336,14 @@ static void intel_plane_clear_hw_state(struct intel_plane_state *plane_state) { if (plane_state->hw.fb) drm_framebuffer_put(plane_state->hw.fb); + if (plane_state->hw.degamma_lut) + drm_property_blob_put(plane_state->hw.degamma_lut); + if (plane_state->hw.gamma_lut) + drm_property_blob_put(plane_state->hw.gamma_lut); + if (plane_state->hw.ctm) + drm_property_blob_put(plane_state->hw.ctm); + if (plane_state->hw.lut_3d) + drm_property_blob_put(plane_state->hw.lut_3d); memset(&plane_state->hw, 0, sizeof(plane_state->hw)); } @@ -434,6 +461,15 @@ void intel_plane_copy_hw_state(struct intel_plane_state *plane_state, if (plane_state->hw.fb) drm_framebuffer_get(plane_state->hw.fb); + + if (plane_state->hw.degamma_lut) + drm_property_blob_get(plane_state->hw.degamma_lut); + if (plane_state->hw.gamma_lut) + drm_property_blob_get(plane_state->hw.gamma_lut); + if (plane_state->hw.ctm) + drm_property_blob_get(plane_state->hw.ctm); + if (plane_state->hw.lut_3d) + drm_property_blob_get(plane_state->hw.lut_3d); } static void unlink_nv12_plane(struct intel_crtc_state *crtc_state, -- 2.25.1