Re: [PATCH] drm/xe: Apply WA_14026810691 to engine

Taylor, Clinton A
2026-04-15T20:18:08Z

On Wed, 2026-04-15 at 12:47 -0700, Matt Roper wrote:
> On Mon, Apr 13, 2026 at 01:08:25PM -0700, Clint Taylor wrote:
> > Apply engine tuning WA_14026810691 starting with IP: Xe3p_LPG
>
> The code changes look good, but I don't think we should refer to
> "WA_14026810691" in the subject and commit message for something that
> isn't actually a workaround and doesn't have an entry in the workaround
> database by that name. If you suggest an alternate wording, I can just
> make the changes while applying the patch; no need to re-submit and
> trigger another CI cycle.
>
New Title:
drm/xe/xe3p: add gt tuning TileY 2x2 walk pattern

-Clint

>
> Matt
>
> > v2: move to xe tunings (MattR)
> > Signed-off-by: Clint Taylor <clinton.a.taylor@intel.com>
> > ---
> > drivers/gpu/drm/xe/regs/xe_gt_regs.h | 3 +++
> > drivers/gpu/drm/xe/xe_tuning.c | 5 +++++
> > 2 files changed, 8 insertions(+)
> >
> > diff --git a/drivers/gpu/drm/xe/regs/xe_gt_regs.h
> > b/drivers/gpu/drm/xe/regs/xe_gt_regs.h
> > index aa267c2f6162..6a16ac1aca96 100644
> > --- a/drivers/gpu/drm/xe/regs/xe_gt_regs.h
> > +++ b/drivers/gpu/drm/xe/regs/xe_gt_regs.h
> > @@ -536,6 +536,9 @@
> > #define SLM_WMTP_RESTORE REG_BIT(11)
> > #define RES_CHK_SPR_DIS REG_BIT(6)
> >
> > +#define TDL_TSL_CHICKEN2 XE_REG_MCR(0xe4cc, XE_REG_OPTION_MASKED)
> > +#define TILEY_LOCALID REG_BIT(2)
> > +
> > #define ROW_CHICKEN XE_REG_MCR(0xe4f0,
> > XE_REG_OPTION_MASKED)
> > #define UGM_BACKUP_MODE REG_BIT(13)
> > #define MDQ_ARBITRATION_MODE REG_BIT(12)
> > diff --git a/drivers/gpu/drm/xe/xe_tuning.c b/drivers/gpu/drm/xe/xe_tuning.c
> > index f8de6a4bf189..39423d5fabcc 100644
> > --- a/drivers/gpu/drm/xe/xe_tuning.c
> > +++ b/drivers/gpu/drm/xe/xe_tuning.c
> > @@ -124,6 +124,11 @@ static const struct xe_rtp_entry_sr engine_tunings[] = {
> > GHWSP_CSB_REPORT_DIS,
> > XE_RTP_ACTION_FLAG(ENGINE_BASE)))
> > },
> > + { XE_RTP_NAME("Tuning: TileY 2x2 Walk"),
> > + XE_RTP_RULES(GRAPHICS_VERSION_RANGE(3510, XE_RTP_END_VERSION_UNDEFINED),
> > + FUNC(xe_rtp_match_first_render_or_compute)),
> > + XE_RTP_ACTIONS(SET(TDL_TSL_CHICKEN2, TILEY_LOCALID))
> > + },
> > };
> >
> > static const struct xe_rtp_entry_sr lrc_tunings[] = {
> > --
> > 2.25.1
> >