Re: [PATCH] drm/xe: Apply WA_14026810691 to engine

Matt Roper
2026-04-09T22:59:05Z

On Thu, Apr 09, 2026 at 02:57:05PM -0700, Clint Taylor wrote:
> Apply WA_14026810691 to following IPs:
> Xe3p_LPG
> Xe3p_XPC
>
> Signed-off-by: Clint Taylor <clinton.a.taylor@intel.com>
> ---
> drivers/gpu/drm/xe/regs/xe_gt_regs.h | 3 +++
> drivers/gpu/drm/xe/xe_wa.c | 6 ++++++
> 2 files changed, 9 insertions(+)
>
> diff --git a/drivers/gpu/drm/xe/regs/xe_gt_regs.h b/drivers/gpu/drm/xe/regs/xe_gt_regs.h
> index aa267c2f6162..6a16ac1aca96 100644
> --- a/drivers/gpu/drm/xe/regs/xe_gt_regs.h
> +++ b/drivers/gpu/drm/xe/regs/xe_gt_regs.h
> @@ -536,6 +536,9 @@
> #define SLM_WMTP_RESTORE REG_BIT(11)
> #define RES_CHK_SPR_DIS REG_BIT(6)
>
> +#define TDL_TSL_CHICKEN2 XE_REG_MCR(0xe4cc, XE_REG_OPTION_MASKED)
> +#define TILEY_LOCALID REG_BIT(2)
> +
> #define ROW_CHICKEN XE_REG_MCR(0xe4f0, XE_REG_OPTION_MASKED)
> #define UGM_BACKUP_MODE REG_BIT(13)
> #define MDQ_ARBITRATION_MODE REG_BIT(12)
> diff --git a/drivers/gpu/drm/xe/xe_wa.c b/drivers/gpu/drm/xe/xe_wa.c
> index 2ec70be78bf9..30dd1687cc8d 100644
> --- a/drivers/gpu/drm/xe/xe_wa.c
> +++ b/drivers/gpu/drm/xe/xe_wa.c
> @@ -609,6 +609,12 @@ static const struct xe_rtp_entry_sr engine_was[] = {
> FUNC(xe_rtp_match_first_render_or_compute)),
> XE_RTP_ACTIONS(SET(ROW_CHICKEN3, DIS_EU_GRF_POISON_TO_LSC))
> },
> + { XE_RTP_NAME("14026810691"),

There doesn't appear to be any record for this in the workaround
database. Looking closer, this appears to be a general (non-workaround)
software programming guidance, currently documented in a programming
note on bspec page 73720:

"SW to set the value to TILEY_2X2 walk pattern"

and also the tuning guide on bspec page 72161:

"Program bit 2 to 1 for all clients to have TileY generated as
2x2 walk pattern"

Since this is a tuning setting rather than a workaround, we should move
the implementation over to the engine_tunings[] table of xe_tuning.c
(and give it a descriptive name like "Tuning: TileY 2x2 Walk" rather
than a number). Also for now this appears to be an open-ended
recommendation that should carry forward to future IP versions as well,
so we can change the range to (3510, XE_RTP_END_VERSION_UNDEFINED) to
match that. If/when the hardware teams eventually change the hardware's
default setting on some future platform down the road, we'll come back
and add a specific upper bound.

Matt

> + XE_RTP_RULES(GRAPHICS_VERSION_RANGE(3510, 3511),
> + FUNC(xe_rtp_match_first_render_or_compute)),
> + XE_RTP_ACTIONS(SET(TDL_TSL_CHICKEN2, TILEY_LOCALID))
> + },
> +
> };
>
> static const struct xe_rtp_entry_sr lrc_was[] = {
> --
> 2.25.1
>

--
Matt Roper
Graphics Software Engineer
Linux GPU Platform Enablement
Intel Corporation