[PATCH 0/3] Xe3p tuning and workaround fixes

[Matt Roper <matthew.d.roper@intel.com>]

The igt@xe_debugfs@check-gt-reg-sr IGT test (which wraps the new
register-save-restore-check debugfs interface) reports that a handful of
reg_sr items are not behaving properly.  In all three cases the report
was correct and highlights some necessary driver fixes.

Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
---
Matt Roper (3):
      drm/xe/tuning: Stop applying CCCHKNREG1 tuning from Xe3p onward
      drm/xe/tuning: Use proper register offset for GAMSTLB_CTRL
      drm/xe: Mark ROW_CHICKEN5 as a masked register

 drivers/gpu/drm/xe/regs/xe_gt_regs.h | 2 +-
 drivers/gpu/drm/xe/xe_tuning.c       | 4 ++--
 2 files changed, 3 insertions(+), 3 deletions(-)
---
base-commit: 8abbd7e03e9925203b7e9cda9b4ea3e3800b74d2
change-id: 20260410-xe3p_tuning-3d5a5ef40dd0

Best regards,
-- 
Matt Roper
Graphics Software Engineer
Linux GPU Platform Enablement
Intel Corporation