[PATCH 3/3] drm/xe/rtp: Fix offset alignment for MERT WHITELIST_OA_MERT_MMIO_TRG

Ashutosh Dixit
2026-04-14T03:52:53Z

'tail_buf' argument for WHITELIST_OA_MERT_MMIO_TRG was previously
wrong (not multiple of 16). Fix this.

Fixes: ec02e49f21bc ("drm/xe/rtp: Whitelist OAMERT MMIO trigger registers")
Signed-off-by: Ashutosh Dixit <ashutosh.dixit@intel.com>
---
drivers/gpu/drm/xe/xe_reg_whitelist.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/xe/xe_reg_whitelist.c b/drivers/gpu/drm/xe/xe_reg_whitelist.c
index 09dcb6a422797..796b3a2b717c0 100644
--- a/drivers/gpu/drm/xe/xe_reg_whitelist.c
+++ b/drivers/gpu/drm/xe/xe_reg_whitelist.c
@@ -106,7 +106,7 @@ static const struct xe_rtp_entry_sr register_whitelist[] = {
OAM_HEAD_POINTER(XE_OAM_SCMI_1_BASE_ADJ))

#define WHITELIST_OA_MERT_MMIO_TRG \
- WHITELIST_OA_MMIO_TRG(OAMERT_MMIO_TRG, OAMERT_HEAD_POINTER)
+ WHITELIST_OA_MMIO_TRG(OAMERT_MMIO_TRG, OAMERT_TAIL_POINTER)

{ XE_RTP_NAME("oag_mmio_trg_rcs"),
XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1200, XE_RTP_END_VERSION_UNDEFINED),
--
2.48.1