Re: [PATCH 3/3] drm/xe/oa: Fix offset alignment for MERT WHITELIST_OA_MERT_MMIO_TRG

Matt Roper
2026-04-15T17:29:24Z

On Tue, Apr 14, 2026 at 08:35:32PM -0700, Ashutosh Dixit wrote:
> 'tail_buf' argument for WHITELIST_OA_MERT_MMIO_TRG was previously
> wrong (not multiple of 16). Fix this.
>
> Fixes: ec02e49f21bc ("drm/xe/rtp: Whitelist OAMERT MMIO trigger registers")
> Signed-off-by: Ashutosh Dixit <ashutosh.dixit@intel.com>
> ---
> drivers/gpu/drm/xe/xe_reg_whitelist.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/xe/xe_reg_whitelist.c b/drivers/gpu/drm/xe/xe_reg_whitelist.c
> index 09dcb6a422797..796b3a2b717c0 100644
> --- a/drivers/gpu/drm/xe/xe_reg_whitelist.c
> +++ b/drivers/gpu/drm/xe/xe_reg_whitelist.c
> @@ -106,7 +106,7 @@ static const struct xe_rtp_entry_sr register_whitelist[] = {
> OAM_HEAD_POINTER(XE_OAM_SCMI_1_BASE_ADJ))
>
> #define WHITELIST_OA_MERT_MMIO_TRG \
> - WHITELIST_OA_MMIO_TRG(OAMERT_MMIO_TRG, OAMERT_HEAD_POINTER)
> + WHITELIST_OA_MMIO_TRG(OAMERT_MMIO_TRG, OAMERT_TAIL_POINTER)

Related to the comments on the previous patch --- if we don't eliminate
the RANGE_4 usage, this whitelists the tail, buffer, and two other
unwanted register offsets beyond that. I don't see anything documented
at those offsets in the bspec right now, but that doesn't mean that it's
okay to expose those to userspace. There could be sensitive SoC
registers located at those offsets, or they could be unused today but
start getting used for something else on an n+1 or n+2 platform. We
need to eliminate the RANGE_4 flag so that we're not granting access to
things we shouldn't be.

I don't know if this whitelisting is even going to work. I seem to
recall that the command streamers might have limits that prevent them
from accessing offsets outside the GT IP (independent of any
whitelist/blacklist handling).

Matt

>
> { XE_RTP_NAME("oag_mmio_trg_rcs"),
> XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1200, XE_RTP_END_VERSION_UNDEFINED),
> --
> 2.48.1
>

--
Matt Roper
Graphics Software Engineer
Linux GPU Platform Enablement
Intel Corporation