From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 7E42BFA0C2D for ; Wed, 15 Apr 2026 05:40:29 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 421C310E676; Wed, 15 Apr 2026 05:40:29 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="kUtSTe3P"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.7]) by gabe.freedesktop.org (Postfix) with ESMTPS id B2BA110E05A; Wed, 15 Apr 2026 05:40:25 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1776231625; x=1807767625; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=5E8kg95mMpogJ7RYneQr/UZ/qVL+Hb4NFSZCXZ4JCJ0=; b=kUtSTe3PKUtNYF/fH0hxuiDeKICRgJmq/duz3SithVtX2p7UNVne+GVT sjWh11ALNXpjdY0foFRHL0kBxjR4HjnIvbmsf/pSRIiQQ1jD3Bg3AISvz bZV5+6j77wbbNCsNqwPJDSboCpEcfmiJTo7UCoaIrMS3M6LkFJZ63sVuC 4Ol5eQzFbOidYhW0JRHzZL+LfV5yHq5P82NAy6rCICL/L6Rlj0G2qRKOH qKS6+aFuNGoYYaBFEm0xdIZDuY66d+DSM+e5PWVtMFCyoZyYNFTL6mBLd 22j2UZzO2FLmoBbHFNV+IXbwYjWhNnTklJ7BPu28JGXnd/4EDK83A+mNO A==; X-CSE-ConnectionGUID: vwvXeoAUQDCpbP7vgzXRMA== X-CSE-MsgGUID: ntPk1sxARUmreeDfeq4m5g== X-IronPort-AV: E=McAfee;i="6800,10657,11759"; a="102657059" X-IronPort-AV: E=Sophos;i="6.23,179,1770624000"; d="scan'208";a="102657059" Received: from fmviesa007.fm.intel.com ([10.60.135.147]) by fmvoesa101.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 14 Apr 2026 22:40:25 -0700 X-CSE-ConnectionGUID: VpO1TclHSIyua9Glngy6Cw== X-CSE-MsgGUID: HV4/9qOsT2uN406RspVPGQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.23,179,1770624000"; d="scan'208";a="227129775" Received: from abityuts-desk.ger.corp.intel.com (HELO jhogande-mobl3.intel.com) ([10.245.244.37]) by fmviesa007-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 14 Apr 2026 22:40:24 -0700 From: =?UTF-8?q?Jouni=20H=C3=B6gander?= To: intel-gfx@lists.freedesktop.org, intel-xe@lists.freedesktop.org Cc: =?UTF-8?q?Jouni=20H=C3=B6gander?= Subject: [PATCH 1/4] drm/i915/psr: Add defininitions for INTEL_WA_REGISTER_CAPS DPCD register Date: Wed, 15 Apr 2026 08:39:57 +0300 Message-ID: <20260415054000.400070-2-jouni.hogander@intel.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260415054000.400070-1-jouni.hogander@intel.com> References: <20260415054000.400070-1-jouni.hogander@intel.com> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Organization: Intel Finland Oy - BIC 0357606-4 - Westendinkatu 7, 02160 Espoo Content-Transfer-Encoding: 8bit X-BeenThere: intel-xe@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel Xe graphics driver List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-xe-bounces@lists.freedesktop.org Sender: "Intel-xe" EDP specification says: "If either VSC SDP is unable to be transmitted 100 ns before the SU region, the Source device may optionally transmit the VSC SDP during the prior video scan line’s HBlank period There is a Intel specific drm dp register currently containing bits related how TCON can support PSR2 with SDP on prior line." Unfortunately many panels are having problems in implementing this. So there is a custom Intel specific DPCD register (INTEL_WA_REGISTER_CAPS) to figure out if this is properly implemented on a panel or if panel doesn't require that 100 ns delay before the SU region. Here are the definitions in this custom DPCD address: 0 = Panel doesn't support SDP on prior line 1 = Panel supports SDP on prior line 2 = Panel doesn't have 100ns requirement 3 = Reserved Add definitions for this new register and it's values into new header intel_dpcd.h. Bspec: 74741 Signed-off-by: Jouni Högander --- drivers/gpu/drm/i915/display/intel_dpcd.h | 15 +++++++++++++++ 1 file changed, 15 insertions(+) create mode 100644 drivers/gpu/drm/i915/display/intel_dpcd.h diff --git a/drivers/gpu/drm/i915/display/intel_dpcd.h b/drivers/gpu/drm/i915/display/intel_dpcd.h new file mode 100644 index 000000000000..670513ff5552 --- /dev/null +++ b/drivers/gpu/drm/i915/display/intel_dpcd.h @@ -0,0 +1,15 @@ +/* SPDX-License-Identifier: MIT */ +/* + * Copyright © 2026 Intel Corporation + */ + +#ifndef __INTEL_DPCD_H__ +#define __INTEL_DPCD_H__ + +#define INTEL_WA_REGISTER_CAPS 0x3f0 +# define INTEL_WA_REGISTER_CAPS_PSR2_EARLYSCANLINE_SDP_SUPPORT_MASK REG_GENMASK(1, 0) +# define INTEL_WA_REGISTER_CAPS_FALL_BACK_TO_PSR1 0 +# define INTEL_WA_REGISTER_CAPS_PSR2_WITH_EARLY_SCANLINE 1 +# define INTEL_WA_REGISTER_CAPS_PSR2_WITHOUT_EARLY_SCANLINE 2 + +#endif /* __INTEL_DPCD_H__ */ -- 2.43.0