[PATCH 4/4] drm/i915/psr: Apply SDP on prior scanline workaround for NVL

Jouni Högander
2026-04-15T05:40:32Z

In NVL there is an HW optimization done. When there is an SU triggered in
Capture state, Link will be kept ON post Capture CRC SDP. Before valid SU
pixels Intel source will transmit dummy pixels. Some TCONS are improperly
considering these dummy pixels as a valid pixel data. Prior NVL link was
was turned of even if there was SU triggered in Capture state and no dummy
pixels were transmitted. These dummy pixels are problem only if SDP on
prior scanline is used and Early Transport is not in use. The workaround is
to start SU area always at scanline 0.

Bspec: 74741, 79482
Signed-off-by: Jouni Högander <jouni.hogander@intel.com>
---
drivers/gpu/drm/i915/display/intel_psr.c | 5 +++++
1 file changed, 5 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
index 341186622ed4..28668fed8347 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.c
+++ b/drivers/gpu/drm/i915/display/intel_psr.c
@@ -2910,6 +2910,11 @@ intel_psr_apply_su_area_workarounds(struct intel_crtc_state *crtc_state)
crtc_state->splitter.enable)
crtc_state->psr2_su_area.y1 = 0;

+ /* Wa_16029024088 */
+ if (DISPLAY_VER(display) >= 35 && crtc_state->req_psr2_sdp_prior_scanline &&
+ !crtc_state->enable_psr2_su_region_et)
+ crtc_state->psr2_su_area.y1 = 0;
+
/* Wa 14019834836 */
if (DISPLAY_VER(display) == 30)
intel_psr_apply_pr_link_on_su_wa(crtc_state);
--
2.43.0