From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id E35E7FA0C2D for ; Wed, 15 Apr 2026 05:40:32 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id A16EB10E67E; Wed, 15 Apr 2026 05:40:32 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="hLp/1AKv"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.7]) by gabe.freedesktop.org (Postfix) with ESMTPS id 2C0D610E67A; Wed, 15 Apr 2026 05:40:30 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1776231630; x=1807767630; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=imhwI7cBkRx6lDeZyqlPNBKKq8ew+w6ck4Jp2syREJo=; b=hLp/1AKv/Fu6u4mWMX7lmrKN13GCwvO+t9fK0WhCBx0P5+23jxV/P+hA sVJvu8aPCtRbtIOPC5Hmlanuvfedz3QzDtoT1jNQn7v9q2om9UHQqkq92 UHFz+YlRKOifTvDea9U6plbRTZLdWDChVrWLtELSgREIom2MFtIGGf4qv hO1KX0bcCM3322vlmknqBpKVAuOJd7lA3waeivIYsAsucwlZ3y90s9PN8 0CzzH0VT1GslciKWwxD854erJaTfx3JDlJRd+e/AXU+s3hqyoad8liled 6HpHRBuhqZvXsqxDhX+Y08SXYjc2FCkcXC2GltsfefNgGxfeRzbE3NfvK A==; X-CSE-ConnectionGUID: AaW11UedTxOQktJkAVZxzA== X-CSE-MsgGUID: VOp7E3ZCRoiHNo1oxTrORQ== X-IronPort-AV: E=McAfee;i="6800,10657,11759"; a="102657064" X-IronPort-AV: E=Sophos;i="6.23,179,1770624000"; d="scan'208";a="102657064" Received: from fmviesa007.fm.intel.com ([10.60.135.147]) by fmvoesa101.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 14 Apr 2026 22:40:30 -0700 X-CSE-ConnectionGUID: 0INnRTCbQOGjgEfa0GrZCw== X-CSE-MsgGUID: +XzSYdTzSlm6+Hutef8Mcw== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.23,179,1770624000"; d="scan'208";a="227129791" Received: from abityuts-desk.ger.corp.intel.com (HELO jhogande-mobl3.intel.com) ([10.245.244.37]) by fmviesa007-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 14 Apr 2026 22:40:29 -0700 From: =?UTF-8?q?Jouni=20H=C3=B6gander?= To: intel-gfx@lists.freedesktop.org, intel-xe@lists.freedesktop.org Cc: =?UTF-8?q?Jouni=20H=C3=B6gander?= Subject: [PATCH 4/4] drm/i915/psr: Apply SDP on prior scanline workaround for NVL Date: Wed, 15 Apr 2026 08:40:00 +0300 Message-ID: <20260415054000.400070-5-jouni.hogander@intel.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260415054000.400070-1-jouni.hogander@intel.com> References: <20260415054000.400070-1-jouni.hogander@intel.com> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Organization: Intel Finland Oy - BIC 0357606-4 - Westendinkatu 7, 02160 Espoo Content-Transfer-Encoding: 8bit X-BeenThere: intel-xe@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel Xe graphics driver List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-xe-bounces@lists.freedesktop.org Sender: "Intel-xe" In NVL there is an HW optimization done. When there is an SU triggered in Capture state, Link will be kept ON post Capture CRC SDP. Before valid SU pixels Intel source will transmit dummy pixels. Some TCONS are improperly considering these dummy pixels as a valid pixel data. Prior NVL link was was turned of even if there was SU triggered in Capture state and no dummy pixels were transmitted. These dummy pixels are problem only if SDP on prior scanline is used and Early Transport is not in use. The workaround is to start SU area always at scanline 0. Bspec: 74741, 79482 Signed-off-by: Jouni Högander --- drivers/gpu/drm/i915/display/intel_psr.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c index 341186622ed4..28668fed8347 100644 --- a/drivers/gpu/drm/i915/display/intel_psr.c +++ b/drivers/gpu/drm/i915/display/intel_psr.c @@ -2910,6 +2910,11 @@ intel_psr_apply_su_area_workarounds(struct intel_crtc_state *crtc_state) crtc_state->splitter.enable) crtc_state->psr2_su_area.y1 = 0; + /* Wa_16029024088 */ + if (DISPLAY_VER(display) >= 35 && crtc_state->req_psr2_sdp_prior_scanline && + !crtc_state->enable_psr2_su_region_et) + crtc_state->psr2_su_area.y1 = 0; + /* Wa 14019834836 */ if (DISPLAY_VER(display) == 30) intel_psr_apply_pr_link_on_su_wa(crtc_state); -- 2.43.0