From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 4A986F557FE for ; Mon, 20 Apr 2026 10:37:27 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 0360110E4C1; Mon, 20 Apr 2026 10:37:27 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="C++4hnp8"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.14]) by gabe.freedesktop.org (Postfix) with ESMTPS id 1050C10E4CA; Mon, 20 Apr 2026 10:37:25 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1776681445; x=1808217445; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=98yzMQg2xvSzjgeqpZUAE0zTxuV4jw13qGfWbbJa1Ds=; b=C++4hnp8l9GToY7tIuAKSQC4tx9ZcZmYW8QcXf0Bsene3rg8uiHs2TdG Z08oJX3hDryTXN5WoEzHxUHXNeVYFInCKJZ76fIIgU83pI9+r5wIXnTjK uA/CmEZiCLFREUmk/98ximnExBS8YmfhqfGa6DJzkvlUD6zfhNvBnbmgj QaFVISBYyXr9VzXY4XmSSLbiXOcoQ1tXl0kppgwFqnPJshCG0T7ROAoCT qwAiptcXx/ZflQxYb1lYVCsbNta3Hw++KM4oC2SmlQmOqcNL5wt6ZQAmJ 744gN059itGJJEpfGVkAbqqK9Y7Ai5RaiWtvXoHt4d3VYjiLCYmX2PN4Z g==; X-CSE-ConnectionGUID: O+WlgoZZRqK9efHh1C4k3A== X-CSE-MsgGUID: vfUhgaznQEWy+QMSmM1iZQ== X-IronPort-AV: E=McAfee;i="6800,10657,11762"; a="81464750" X-IronPort-AV: E=Sophos;i="6.23,189,1770624000"; d="scan'208";a="81464750" Received: from orviesa009.jf.intel.com ([10.64.159.149]) by orvoesa106.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 20 Apr 2026 03:37:25 -0700 X-CSE-ConnectionGUID: UFkFsF5/QTytrdYIc+L/mg== X-CSE-MsgGUID: 8iDyssaPSjOLIPBOK5QNfw== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.23,189,1770624000"; d="scan'208";a="231554566" Received: from vpanait-mobl.ger.corp.intel.com (HELO hazy.intel.com) ([10.245.244.99]) by orviesa009-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 20 Apr 2026 03:37:22 -0700 From: Luca Coelho To: intel-gfx@lists.freedesktop.org Cc: intel-xe@lists.freedesktop.org, jani.nikula@linux.intel.com, ville.syrjala@linux.intel.com Subject: [PATCH v3 1/8] drm/i915: move SKL clock gating init to display Date: Mon, 20 Apr 2026 13:30:43 +0300 Message-ID: <20260420103705.3453499-2-luciano.coelho@intel.com> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20260420103705.3453499-1-luciano.coelho@intel.com> References: <20260420103705.3453499-1-luciano.coelho@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-BeenThere: intel-xe@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel Xe graphics driver List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-xe-bounces@lists.freedesktop.org Sender: "Intel-xe" Move the SKL-specific display clock gating programming into a new file inside display. This removes dependency from intel_clock_gating.c to the display's intel_pch.h file, so we can remove the include statement. Signed-off-by: Luca Coelho --- drivers/gpu/drm/i915/Makefile | 1 + .../i915/display/intel_display_clock_gating.c | 19 +++++++++++++++++++ .../i915/display/intel_display_clock_gating.h | 13 +++++++++++++ drivers/gpu/drm/i915/intel_clock_gating.c | 8 ++------ 4 files changed, 35 insertions(+), 6 deletions(-) create mode 100644 drivers/gpu/drm/i915/display/intel_display_clock_gating.c create mode 100644 drivers/gpu/drm/i915/display/intel_display_clock_gating.h diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile index b677720a1c2d..63a9e16826a9 100644 --- a/drivers/gpu/drm/i915/Makefile +++ b/drivers/gpu/drm/i915/Makefile @@ -255,6 +255,7 @@ i915-y += \ display/intel_cursor.o \ display/intel_dbuf_bw.o \ display/intel_de.o \ + display/intel_display_clock_gating.o \ display/intel_display.o \ display/intel_display_conversion.o \ display/intel_display_driver.o \ diff --git a/drivers/gpu/drm/i915/display/intel_display_clock_gating.c b/drivers/gpu/drm/i915/display/intel_display_clock_gating.c new file mode 100644 index 000000000000..4a94593335e0 --- /dev/null +++ b/drivers/gpu/drm/i915/display/intel_display_clock_gating.c @@ -0,0 +1,19 @@ +// SPDX-License-Identifier: MIT +/* + * Copyright 2026 Intel Corporation + */ + +#include + +#include "intel_de.h" +#include "intel_display_clock_gating.h" +#include "intel_display_regs.h" + +void intel_display_skl_init_clock_gating(struct intel_display *display) +{ + /* + * WaFbcTurnOffFbcWatermark:skl + * Display WA #0562: skl + */ + intel_de_rmw(display, DISP_ARB_CTL, 0, DISP_FBC_WM_DIS); +} diff --git a/drivers/gpu/drm/i915/display/intel_display_clock_gating.h b/drivers/gpu/drm/i915/display/intel_display_clock_gating.h new file mode 100644 index 000000000000..00f416db7f47 --- /dev/null +++ b/drivers/gpu/drm/i915/display/intel_display_clock_gating.h @@ -0,0 +1,13 @@ +/* SPDX-License-Identifier: MIT */ +/* + * Copyright 2026 Intel Corporation + */ + +#ifndef __INTEL_DISPLAY_CLOCK_GATING_H__ +#define __INTEL_DISPLAY_CLOCK_GATING_H__ + +struct intel_display; + +void intel_display_skl_init_clock_gating(struct intel_display *display); + +#endif /* __INTEL_DISPLAY_CLOCK_GATING_H__ */ diff --git a/drivers/gpu/drm/i915/intel_clock_gating.c b/drivers/gpu/drm/i915/intel_clock_gating.c index ee2489a2fbe7..454334fef5e7 100644 --- a/drivers/gpu/drm/i915/intel_clock_gating.c +++ b/drivers/gpu/drm/i915/intel_clock_gating.c @@ -31,9 +31,9 @@ #include "display/i9xx_plane_regs.h" #include "display/intel_display.h" +#include "display/intel_display_clock_gating.h" #include "display/intel_display_core.h" #include "display/intel_display_regs.h" -#include "display/intel_pch.h" #include "gt/intel_engine_regs.h" #include "gt/intel_gt.h" #include "gt/intel_gt_mcr.h" @@ -349,11 +349,7 @@ static void skl_init_clock_gating(struct drm_i915_private *i915) /* WAC6entrylatency:skl */ intel_uncore_rmw(&i915->uncore, FBC_LLC_READ_CTRL, 0, FBC_LLC_FULLY_OPEN); - /* - * WaFbcTurnOffFbcWatermark:skl - * Display WA #0562: skl - */ - intel_uncore_rmw(&i915->uncore, DISP_ARB_CTL, 0, DISP_FBC_WM_DIS); + intel_display_skl_init_clock_gating(i915->display); } static void bdw_init_clock_gating(struct drm_i915_private *i915) -- 2.53.0