[PATCH 05/10] drm/xe: Fix name and definition of GFX_MODE register

Matt Roper
2026-04-23T22:49:09Z

The register located at $base+0x29c is referred to as GFX_MODE in the
bspec. Although many other registers have RING_* prefixes for
historical reasons, this register does not, so using a name that does
not match the bspec just makes it harder to recognize/find.

Also, GFX_MODE is a masked register (updating bits [15:0] requires that
the corresponding bit(s) in [31:16] are also set), so add the
XE_REG_OPTION_MASKED flag to the register definition; this will become
important when we start programming this register via RTP tables in a
future patch.

Finally swap the order of the register's two bit definitions to match
our regular coding style of descending order for register bits/fields.

Bspec: 45928
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
---
drivers/gpu/drm/xe/regs/xe_engine_regs.h | 4 ++--
drivers/gpu/drm/xe/xe_execlist.c | 2 +-
drivers/gpu/drm/xe/xe_guc_ads.c | 2 +-
drivers/gpu/drm/xe/xe_guc_capture.c | 2 +-
drivers/gpu/drm/xe/xe_hw_engine.c | 2 +-
5 files changed, 6 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/xe/regs/xe_engine_regs.h b/drivers/gpu/drm/xe/regs/xe_engine_regs.h
index 1b4a7e9a703d..4d5cd1b6f50d 100644
--- a/drivers/gpu/drm/xe/regs/xe_engine_regs.h
+++ b/drivers/gpu/drm/xe/regs/xe_engine_regs.h
@@ -165,9 +165,9 @@
#define CTX_CTRL_INHIBIT_SYN_CTX_SWITCH REG_BIT(3)
#define CTX_CTRL_ENGINE_CTX_RESTORE_INHIBIT REG_BIT(0)

-#define RING_MODE(base) XE_REG((base) + 0x29c)
-#define GFX_DISABLE_LEGACY_MODE REG_BIT(3)
+#define GFX_MODE(base) XE_REG((base) + 0x29c, XE_REG_OPTION_MASKED)
#define GFX_MSIX_INTERRUPT_ENABLE REG_BIT(13)
+#define GFX_DISABLE_LEGACY_MODE REG_BIT(3)

#define RING_CSMQDEBUG(base) XE_REG((base) + 0x2b0)

diff --git a/drivers/gpu/drm/xe/xe_execlist.c b/drivers/gpu/drm/xe/xe_execlist.c
index 026a1ec0c868..337b9b4e8b4a 100644
--- a/drivers/gpu/drm/xe/xe_execlist.c
+++ b/drivers/gpu/drm/xe/xe_execlist.c
@@ -80,7 +80,7 @@ static void __start_lrc(struct xe_hw_engine *hwe, struct xe_lrc *lrc,

if (xe_device_has_msix(gt_to_xe(hwe->gt)))
ring_mode |= REG_MASKED_FIELD_ENABLE(GFX_MSIX_INTERRUPT_ENABLE);
- xe_mmio_write32(mmio, RING_MODE(hwe->mmio_base), ring_mode);
+ xe_mmio_write32(mmio, GFX_MODE(hwe->mmio_base), ring_mode);

xe_mmio_write32(mmio, RING_EXECLIST_SQ_CONTENTS_LO(hwe->mmio_base),
lower_32_bits(lrc_desc));
diff --git a/drivers/gpu/drm/xe/xe_guc_ads.c b/drivers/gpu/drm/xe/xe_guc_ads.c
index d0497d9f43a2..b403ee0b5e74 100644
--- a/drivers/gpu/drm/xe/xe_guc_ads.c
+++ b/drivers/gpu/drm/xe/xe_guc_ads.c
@@ -745,7 +745,7 @@ static unsigned int guc_mmio_regset_write(struct xe_guc_ads *ads,
struct xe_reg reg;
bool skip;
} *e, extra_regs[] = {
- { .reg = RING_MODE(hwe->mmio_base), },
+ { .reg = GFX_MODE(hwe->mmio_base), },
{ .reg = RING_HWS_PGA(hwe->mmio_base), },
{ .reg = RING_IMR(hwe->mmio_base), },
{ .reg = CCS_MODE,
diff --git a/drivers/gpu/drm/xe/xe_guc_capture.c b/drivers/gpu/drm/xe/xe_guc_capture.c
index 2f5816c78fba..bc49e40165a3 100644
--- a/drivers/gpu/drm/xe/xe_guc_capture.c
+++ b/drivers/gpu/drm/xe/xe_guc_capture.c
@@ -111,7 +111,7 @@ struct __guc_capture_parsed_output {
{ RING_TAIL(0), REG_32BIT, 0, 0, 0, "RING_TAIL"}, \
{ RING_CTL(0), REG_32BIT, 0, 0, 0, "RING_CTL"}, \
{ RING_MI_MODE(0), REG_32BIT, 0, 0, 0, "RING_MI_MODE"}, \
- { RING_MODE(0), REG_32BIT, 0, 0, 0, "RING_MODE"}, \
+ { GFX_MODE(0), REG_32BIT, 0, 0, 0, "GFX_MODE"}, \
{ RING_ESR(0), REG_32BIT, 0, 0, 0, "RING_ESR"}, \
{ RING_EMR(0), REG_32BIT, 0, 0, 0, "RING_EMR"}, \
{ RING_EIR(0), REG_32BIT, 0, 0, 0, "RING_EIR"}, \
diff --git a/drivers/gpu/drm/xe/xe_hw_engine.c b/drivers/gpu/drm/xe/xe_hw_engine.c
index 06eb655a4ae5..d28f50a64d88 100644
--- a/drivers/gpu/drm/xe/xe_hw_engine.c
+++ b/drivers/gpu/drm/xe/xe_hw_engine.c
@@ -332,7 +332,7 @@ void xe_hw_engine_enable_ring(struct xe_hw_engine *hwe)

if (xe_device_has_msix(gt_to_xe(hwe->gt)))
ring_mode |= REG_MASKED_FIELD_ENABLE(GFX_MSIX_INTERRUPT_ENABLE);
- xe_hw_engine_mmio_write32(hwe, RING_MODE(0), ring_mode);
+ xe_hw_engine_mmio_write32(hwe, GFX_MODE(0), ring_mode);
xe_hw_engine_mmio_write32(hwe, RING_MI_MODE(0),
REG_MASKED_FIELD_DISABLE(STOP_RING));
xe_hw_engine_mmio_read32(hwe, RING_MI_MODE(0));

--
2.53.0