From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 2A3D5FF8870 for ; Tue, 28 Apr 2026 07:59:41 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 3BE8C10EA5C; Tue, 28 Apr 2026 07:59:40 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="kk8d4dnC"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.12]) by gabe.freedesktop.org (Postfix) with ESMTPS id B291810EA5C; Tue, 28 Apr 2026 07:59:39 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1777363179; x=1808899179; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=/FTMmu33X/1By3IOADJAh7WnITIuRCYMTTOsIDIUYcI=; b=kk8d4dnC6oQzEG1bWVUBTc4WqKxzR425obcTvfstSWV1gWtpgQAtkRH3 qxHsEu17viAVT1XnO2XqHBQ8e8UFUopv4JgEaCNbAYhaQ3WL4+OjxaCoE MgQqPgr7PySH2IUsvvgjqQ1zzEn7cGq5t/OetXo/AeKJ/tzNTC7u2V8Ie b0HYbaanwNm7FL0higAT8YiP6d3xxead01+dXLsU4T7pJSN8H2Lys7Q9w trlLJHZSncU/R6N8H8xbyYq8FioGey0L2NOlhqG4ZxlmfIZowTxOpGXzw YYTNToDN0DVVlb0AXo/L8ifvV4ypN5ioBZNo9kKxda4hJvmLAwR8Fr5x6 w==; X-CSE-ConnectionGUID: 02wSr6QBRfSAi6lEz4m8Tw== X-CSE-MsgGUID: MF904iT7RgS8tH2M9A8SIQ== X-IronPort-AV: E=McAfee;i="6800,10657,11769"; a="82115898" X-IronPort-AV: E=Sophos;i="6.23,203,1770624000"; d="scan'208";a="82115898" Received: from fmviesa003.fm.intel.com ([10.60.135.143]) by fmvoesa106.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 28 Apr 2026 00:59:39 -0700 X-CSE-ConnectionGUID: g6zhCMvlRNWxQkxFS2FnqQ== X-CSE-MsgGUID: 6OowHiNySn6y3kEhG4buSA== X-ExtLoop1: 1 Received: from srr4-3-linux-103-aknautiy.iind.intel.com ([10.223.34.160]) by fmviesa003-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 28 Apr 2026 00:59:37 -0700 From: Ankit Nautiyal To: intel-gfx@lists.freedesktop.org, intel-xe@lists.freedesktop.org, dri-devel@lists.freedesktop.org Cc: ville.syrjala@linux.intel.com, jani.nikula@linux.intel.com, Ankit Nautiyal Subject: [PATCH 1/9] drm/dp: Rename and relocate AS SDP payload field masks Date: Tue, 28 Apr 2026 13:14:49 +0530 Message-ID: <20260428074457.3566918-2-ankit.k.nautiyal@intel.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20260428074457.3566918-1-ankit.k.nautiyal@intel.com> References: <20260428074457.3566918-1-ankit.k.nautiyal@intel.com> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-BeenThere: intel-xe@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel Xe graphics driver List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-xe-bounces@lists.freedesktop.org Sender: "Intel-xe" The AS SDP payload field masks were misnamed and placed under the DPRX feature enumeration list. These are not DPRX capability bits, but are payload field masks for the Adaptive Sync SDP. Relocate both masks next to the AS SDP definitions. Update users to the corrected names. No functional change. Signed-off-by: Ankit Nautiyal Reviewed-by: Ville Syrjälä --- drivers/gpu/drm/i915/display/intel_dp.c | 4 ++-- include/drm/display/drm_dp.h | 5 +++-- 2 files changed, 5 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c index 8631df908b07..0d15e813ba71 100644 --- a/drivers/gpu/drm/i915/display/intel_dp.c +++ b/drivers/gpu/drm/i915/display/intel_dp.c @@ -5354,8 +5354,8 @@ int intel_dp_as_sdp_unpack(struct drm_dp_as_sdp *as_sdp, if ((sdp->sdp_header.HB3 & 0x3F) != 9) return -EINVAL; - as_sdp->length = sdp->sdp_header.HB3 & DP_ADAPTIVE_SYNC_SDP_LENGTH; - as_sdp->mode = sdp->db[0] & DP_ADAPTIVE_SYNC_SDP_OPERATION_MODE; + as_sdp->length = sdp->sdp_header.HB3 & DP_AS_SDP_LENGTH_MASK; + as_sdp->mode = sdp->db[0] & DP_AS_SDP_OPERATION_MODE_MASK; as_sdp->vtotal = (sdp->db[2] << 8) | sdp->db[1]; as_sdp->target_rr = (u64)sdp->db[3] | ((u64)sdp->db[4] & 0x3); as_sdp->target_rr_divider = sdp->db[4] & 0x20 ? true : false; diff --git a/include/drm/display/drm_dp.h b/include/drm/display/drm_dp.h index 8b15d3eeb716..4ea3b5b08a12 100644 --- a/include/drm/display/drm_dp.h +++ b/include/drm/display/drm_dp.h @@ -1204,8 +1204,6 @@ #define DP_DPRX_FEATURE_ENUMERATION_LIST_CONT_1 0x2214 /* 2.0 E11 */ # define DP_ADAPTIVE_SYNC_SDP_SUPPORTED (1 << 0) -# define DP_ADAPTIVE_SYNC_SDP_OPERATION_MODE GENMASK(1, 0) -# define DP_ADAPTIVE_SYNC_SDP_LENGTH GENMASK(5, 0) # define DP_AS_SDP_FIRST_HALF_LINE_OR_3840_PIXEL_CYCLE_WINDOW_NOT_SUPPORTED (1 << 1) # define DP_VSC_EXT_SDP_FRAMEWORK_VERSION_1_SUPPORTED (1 << 4) @@ -1870,4 +1868,7 @@ enum operation_mode { DP_AS_SDP_FAVT_TRR_REACHED = 0x03 }; +#define DP_AS_SDP_OPERATION_MODE_MASK GENMASK(1, 0) +#define DP_AS_SDP_LENGTH_MASK GENMASK(5, 0) + #endif /* _DRM_DP_H_ */ -- 2.45.2