From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id A16D1FF885A for ; Tue, 28 Apr 2026 07:59:48 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 599E610EA6A; Tue, 28 Apr 2026 07:59:48 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="ID9vlC6X"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.12]) by gabe.freedesktop.org (Postfix) with ESMTPS id CCF8C10EA61; Tue, 28 Apr 2026 07:59:41 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1777363181; x=1808899181; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=XjDIcelhTBrb67a2mZBXv/6E7BGm3pawrsiQbz/4hlI=; b=ID9vlC6X+QKtNdBrUA9rC4X6pLlk6JimNz21netVYIgcMHneEwwdHJWg U7Il5VdGcLONEmy+X2/Ny1J5Ezs1lYXkYp5iO524y/3OFq1ZX5mxuvnz6 Y+EFMZe4av5ut8PJNrBhn6afLeHxvd1YJ7KqBFyDG/lPSkIDMfSnEppwI fb2rnyywaf5PavAhe+psqBsSD3RRGyIQ+HsBzYCFZpLI7vSYd26CwBVvj gSp3K1o/IY26wQj/aDIQ+7gmc8ZwFeSRldmi6qe/VgTXBN+3StaDssapu gkTmyDtBsGWg4ABCZeC0FRvOY79MA4vqf0zVzGpU8qrS5WUnSowX0om/S w==; X-CSE-ConnectionGUID: /aa1AVycSZaZnVaS7JKn1A== X-CSE-MsgGUID: tf21WjjbSVGkaneOE2xRhg== X-IronPort-AV: E=McAfee;i="6800,10657,11769"; a="82115899" X-IronPort-AV: E=Sophos;i="6.23,203,1770624000"; d="scan'208";a="82115899" Received: from fmviesa003.fm.intel.com ([10.60.135.143]) by fmvoesa106.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 28 Apr 2026 00:59:41 -0700 X-CSE-ConnectionGUID: WzgBdZd1SSqgZb4fvNF1qg== X-CSE-MsgGUID: IAy0aQZmQvyfVgXQ28WVnw== X-ExtLoop1: 1 Received: from srr4-3-linux-103-aknautiy.iind.intel.com ([10.223.34.160]) by fmviesa003-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 28 Apr 2026 00:59:39 -0700 From: Ankit Nautiyal To: intel-gfx@lists.freedesktop.org, intel-xe@lists.freedesktop.org, dri-devel@lists.freedesktop.org Cc: ville.syrjala@linux.intel.com, jani.nikula@linux.intel.com, Ankit Nautiyal Subject: [PATCH 2/9] drm/dp: Clean up DPRX feature enumeration macros Date: Tue, 28 Apr 2026 13:14:50 +0530 Message-ID: <20260428074457.3566918-3-ankit.k.nautiyal@intel.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20260428074457.3566918-1-ankit.k.nautiyal@intel.com> References: <20260428074457.3566918-1-ankit.k.nautiyal@intel.com> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-BeenThere: intel-xe@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel Xe graphics driver List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-xe-bounces@lists.freedesktop.org Sender: "Intel-xe" Align the DP_DPRX feature enumeration macros for better readability and consistency, and use the BIT() macro instead of open-coded shifts. Signed-off-by: Ankit Nautiyal Reviewed-by: Ville Syrjälä --- include/drm/display/drm_dp.h | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/include/drm/display/drm_dp.h b/include/drm/display/drm_dp.h index 4ea3b5b08a12..49f0154eb93c 100644 --- a/include/drm/display/drm_dp.h +++ b/include/drm/display/drm_dp.h @@ -1202,10 +1202,10 @@ # define DP_DPRX_SLEEP_WAKE_TIMEOUT_PERIOD_80_MS 0x04 # define DP_DPRX_SLEEP_WAKE_TIMEOUT_PERIOD_100_MS 0x05 -#define DP_DPRX_FEATURE_ENUMERATION_LIST_CONT_1 0x2214 /* 2.0 E11 */ -# define DP_ADAPTIVE_SYNC_SDP_SUPPORTED (1 << 0) -# define DP_AS_SDP_FIRST_HALF_LINE_OR_3840_PIXEL_CYCLE_WINDOW_NOT_SUPPORTED (1 << 1) -# define DP_VSC_EXT_SDP_FRAMEWORK_VERSION_1_SUPPORTED (1 << 4) +#define DP_DPRX_FEATURE_ENUMERATION_LIST_CONT_1 0x2214 /* 2.0 E11 */ +# define DP_ADAPTIVE_SYNC_SDP_SUPPORTED BIT(0) +# define DP_AS_SDP_FIRST_HALF_LINE_OR_3840_PIXEL_CYCLE_WINDOW_NOT_SUPPORTED BIT(1) +# define DP_VSC_EXT_SDP_FRAMEWORK_VERSION_1_SUPPORTED BIT(4) #define DP_128B132B_SUPPORTED_LINK_RATES 0x2215 /* 2.0 */ # define DP_UHBR10 (1 << 0) -- 2.45.2