From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id E9356FF885D for ; Tue, 28 Apr 2026 07:59:49 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 9A77010EA6C; Tue, 28 Apr 2026 07:59:49 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="EyGhuCmH"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.12]) by gabe.freedesktop.org (Postfix) with ESMTPS id 44E7710EA66; Tue, 28 Apr 2026 07:59:46 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1777363186; x=1808899186; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=dZmKkKLikUTl7wjGHZFppVc8YNoDPQ6scOWogV/niw4=; b=EyGhuCmHxBmJXgqZ/AP9wQoO1fOWYvGDcnEZf9fDOotGCNVF6yH6uX3Y XrSXZYKZKEgsUkJapimFVPbOWZ2Y42Fsd95l+LYmpiFbS/j+wjKjq3de+ uG+hv1sjeY8UnT+xbagkqlohNkC0p8rcjvyYC+9I8EKdBtckONFIIxdIZ WeAMi16L03uI5KafBANAp0eqk++kxsTlXTNv/ZSnuwl1LKhWF7tYRhit7 Ip5qQHWdHUXycpgyDVc0PI+qkSGt2mT/ZW1Z/p4HATHXMCr9nhPyfjl4n tRmusZ+Pi0+wzSXbID/QL5s9EGyzzNrb5DKtatLYaJnUEiooKi10KNw8V A==; X-CSE-ConnectionGUID: 3hBC3xqyT1CguY4dSpZWRQ== X-CSE-MsgGUID: KKjybaDDSc66ahB85QVyFA== X-IronPort-AV: E=McAfee;i="6800,10657,11769"; a="82115904" X-IronPort-AV: E=Sophos;i="6.23,203,1770624000"; d="scan'208";a="82115904" Received: from fmviesa003.fm.intel.com ([10.60.135.143]) by fmvoesa106.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 28 Apr 2026 00:59:46 -0700 X-CSE-ConnectionGUID: n9FqoJ5rQbKVdqeEsugcew== X-CSE-MsgGUID: pp/Y/dX8RNyH/DbrV4AW8g== X-ExtLoop1: 1 Received: from srr4-3-linux-103-aknautiy.iind.intel.com ([10.223.34.160]) by fmviesa003-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 28 Apr 2026 00:59:44 -0700 From: Ankit Nautiyal To: intel-gfx@lists.freedesktop.org, intel-xe@lists.freedesktop.org, dri-devel@lists.freedesktop.org Cc: ville.syrjala@linux.intel.com, jani.nikula@linux.intel.com, Ankit Nautiyal Subject: [PATCH 4/9] drm/dp: Add DPCD for configuring AS SDP for PR + VRR Date: Tue, 28 Apr 2026 13:14:52 +0530 Message-ID: <20260428074457.3566918-5-ankit.k.nautiyal@intel.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20260428074457.3566918-1-ankit.k.nautiyal@intel.com> References: <20260428074457.3566918-1-ankit.k.nautiyal@intel.com> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-BeenThere: intel-xe@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel Xe graphics driver List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-xe-bounces@lists.freedesktop.org Sender: "Intel-xe" Add additional DPCDs required to be configured to support VRR with Panel Replay. These DPCDs are specifically required for configuring Adaptive Sync SDP and are introduced in DP v2.1. v2: - Correct the shift for the bits. (Ville) - Add DP_PR_ prefix for the PR-related fields. v3: - Use macro values in their shifted form to match the convention. (Ville) v4: - Add macro for the mask. (Ville) Signed-off-by: Ankit Nautiyal Reviewed-by: Ville Syrjälä --- include/drm/display/drm_dp.h | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/include/drm/display/drm_dp.h b/include/drm/display/drm_dp.h index 8d172863eba3..829e4d98d61c 100644 --- a/include/drm/display/drm_dp.h +++ b/include/drm/display/drm_dp.h @@ -718,6 +718,12 @@ #define DP_EXTENDED_DPRX_SLEEP_WAKE_TIMEOUT_GRANT 0x119 /* 1.4a */ # define DP_DPRX_SLEEP_WAKE_TIMEOUT_PERIOD_GRANTED (1 << 0) +#define PANEL_REPLAY_CONFIG3 0x11a /* DP 2.1 */ +# define DP_PR_AS_SDP_SETUP_TIME_MASK (3 << 6) +# define DP_PR_AS_SDP_SETUP_TIME_T1 (0 << 6) +# define DP_PR_AS_SDP_SETUP_TIME_DYNAMIC (1 << 6) /* DP 2.1 Table 2-227 */ +# define DP_PR_AS_SDP_SETUP_TIME_T2 (2 << 6) + #define DP_FEC_CONFIGURATION 0x120 /* 1.4 */ # define DP_FEC_READY (1 << 0) # define DP_FEC_ERR_COUNT_SEL_MASK (7 << 1) -- 2.45.2