[PATCH] drm/xe: Add memory barrier before H2G tail write on wrap

[Matthew Brost <matthew.brost@intel.com>]

When the H2G buffer wraps, it is padded with NOPs before updating the
H2G descriptor tail. However, the tail update is performed without a
memory barrier, allowing the GuC to observe the new tail value before
the NOP writes become visible.
 
This can result in the GuC reading stale H2G commands, potentially
causing a variety of failures. Fix this by inserting a memory barrier
before updating the H2G descriptor tail.

Fixes: dd08ebf6c352 ("drm/xe: Introduce a new DRM driver for Intel GPUs")
Cc: stable@vger.kernel.org
Reported-by: Sashiko <sashiko-bot@kernel.org>
Signed-off-by: Matthew Brost <matthew.brost@intel.com>
---
 drivers/gpu/drm/xe/xe_guc_ct.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/gpu/drm/xe/xe_guc_ct.c b/drivers/gpu/drm/xe/xe_guc_ct.c
index fe70c0fd85c5..49031497e9dd 100644
--- a/drivers/gpu/drm/xe/xe_guc_ct.c
+++ b/drivers/gpu/drm/xe/xe_guc_ct.c
@@ -993,6 +993,7 @@ static int h2g_write(struct xe_guc_ct *ct, const u32 *action, u32 len,
 			      (h2g->info.size - tail) * sizeof(u32));
 		h2g_reserve_space(ct, (h2g->info.size - tail));
 		h2g->info.tail = 0;
+		xe_device_wmb(xe);
 		desc_write(xe, h2g, tail, h2g->info.tail);
 
 		return -EAGAIN;
-- 
2.34.1