[PATCH 00/44] Enable HDMI FRL for MTL+

[Ankit Nautiyal <ankit.k.nautiyal@intel.com>]

This series adds support for HDMI Fixed Rate Link (FRL) on MTL+ platforms.
FRL is a high-bandwidth transmission mode required for modes that exceed
the TMDS bandwidth limit.

The series covers the core enabling:
- SCDC helper additions for FRL link training
- FRL link training state machine (LTS:2, LTS:3, LTS:P)
- DDI enable/disable sequence updates for FRL mode
- DFM (Data Flow Metering) computation and register programming
- PHY (CX0/LT PHY) support for FRL rates
- Mode validation and clock computation for FRL

This is a work in progress. The primary goal at this stage is to get the
overall design reviewed and the foundational patches landed before building
on top.

Lightly tested on PTL. Modes like 4K@120 are working. Higher resolution
modes (e.g. 8K) require DSC which is not yet covered in this series, that
work is ongoing.

Testing on other MTL+ platforms is also ongoing.
Known gaps:
- DSC over FRL not yet supported
- Testing limited to MTL, PTL so far

Feedback on the design and approach is welcome.

Ankit Nautiyal (28):
  drm/i915/hdmi: Add new data members for FRL configuration
  drm/i915/hdmi: Add FRL link rate cap
  drm/drm_scdc_helper: Add SCDC helper funcs for FRL
  drm/i915/display: Add registers for HDMI FRL configuration
  drm/i915/display: Add new members in crtc_state for FRL configuration
  drm/i915/intel_cx0_phy_regs: Add HDMI FRL SHIFT EN bit in
    PORT_BUF_CTL_1
  drm/i915/ddi: Update Transcoder/DDI registers with the frl bits
  drm/i915/hdmi: Enable Scrambling only for TMDS mode
  drm/i915/ddi: Simplify intel_ddi_enable()
  drm/i915/ddi: Factor out common transcoder/vblank enable sequence
  drm/i915/ddi: Update HDMI modeset sequence for MTL+
  drm/i915/hdmi: Add function to prepare registers for FRL mode
  drm/i915/hdmi: Add functions for FRL training state machine
  drm/i915/intel_hdmi: Add helper to disable FRL
  drm/i915/hdmi: Reduce FRL rate cap on rate change during training
  drm/i915/hdmi: Add provision for FRL mode while computing output
    format
  drm/i915/cx0: Add helper to check if the FRL rate is valid
  drm/i915/lt_phy: Add helper to check if the FRL rate is valid
  drm/i915/hdmi_frl_dfm: Add support for DFM calculation with DSC
  drm/i915/hdmi: Add helper to write FRL CFG register
  drm/i915/hdmi_frl_dfm: Add helpers to read/write FRL DFM registers
  drm/i915/hdmi_frl_dfm: Add function to compute FRL DFM config
  drm/i915/hdmi: Add FRL clock computation based on DFM
  drm/i915/hdmi: Add support for sending uevent to user for FRL training
    failure
  drm/i915/ddi: Wire FRL into the HDMI DDI enable/disable path
  drm/i915/hdmi: Add read out for FRL state
  drm/i915/display: Add FRL members to the state checker
  drm/i915/hdmi: Compute output format for HDMI FRL mode

Suraj Kandpal (7):
  drm/i915/hdmi: Introduce intel_hdmi_frl_level() for per-lane TxFFE
  drm/i915/hdmi: Drive per-lane TxFFE during FRL link training
  drm/i915/ltphy: Add PLL tables for HDMI FRL
  drm/i915/ltphy: Add safegaurd when calculation HDMI FRL state
  drm/i915/ltphy: Calculate port clock for HDMI FRL
  drm/i915/ltphy: Verify HDMI FRL tables
  drm/i915/ddi_buf: Add Vswing table for HDMI FRL

Vandita Kulkarni (9):
  drm/i915/hdmi: Parse frl max link rate from vbt
  drm/i915/hdmi: Rename port clock limit to specify tmds clock
  drm/i915/hdmi: Rename port clock valid to specify tmds clock
  drm/i915/hdmi: Add FRL port and mode clock valid
  drm/i915/hdmi_frl_dfm_regs: Define DFM registers
  drm/i915/hdmi_frl_dfm: Define frl_dfm structure
  drm/i915/hdmi_frl_dfm: Add non dsc frl capacity computation helpers
  drm/i915/hdmi_frl_dfm: Handle FRL Link M/N
  drm/i915/hdmi: Enable FRL based mode clock valid

 drivers/gpu/drm/display/drm_scdc_helper.c     | 212 +++++
 drivers/gpu/drm/i915/Makefile                 |   1 +
 drivers/gpu/drm/i915/display/intel_bios.c     |  53 ++
 drivers/gpu/drm/i915/display/intel_bios.h     |   1 +
 drivers/gpu/drm/i915/display/intel_cx0_phy.c  |  23 +
 drivers/gpu/drm/i915/display/intel_cx0_phy.h  |   1 +
 .../gpu/drm/i915/display/intel_cx0_phy_regs.h |   1 +
 drivers/gpu/drm/i915/display/intel_ddi.c      | 162 +++-
 .../drm/i915/display/intel_ddi_buf_trans.c    |  25 +
 drivers/gpu/drm/i915/display/intel_display.c  |   9 +
 .../gpu/drm/i915/display/intel_display_regs.h |  26 +
 .../drm/i915/display/intel_display_types.h    |  38 +
 drivers/gpu/drm/i915/display/intel_hdmi.c     | 808 +++++++++++++++-
 drivers/gpu/drm/i915/display/intel_hdmi.h     |  14 +-
 .../gpu/drm/i915/display/intel_hdmi_frl_dfm.c | 892 ++++++++++++++++++
 .../gpu/drm/i915/display/intel_hdmi_frl_dfm.h | 126 +++
 .../i915/display/intel_hdmi_frl_dfm_regs.h    |  36 +
 drivers/gpu/drm/i915/display/intel_lt_phy.c   | 315 ++++++-
 drivers/gpu/drm/i915/display/intel_lt_phy.h   |   1 +
 drivers/gpu/drm/i915/display/intel_vbt_defs.h |   7 +
 drivers/gpu/drm/xe/Makefile                   |   1 +
 include/drm/display/drm_scdc.h                |  26 +
 include/drm/display/drm_scdc_helper.h         |  22 +
 23 files changed, 2704 insertions(+), 96 deletions(-)
 create mode 100644 drivers/gpu/drm/i915/display/intel_hdmi_frl_dfm.c
 create mode 100644 drivers/gpu/drm/i915/display/intel_hdmi_frl_dfm.h
 create mode 100644 drivers/gpu/drm/i915/display/intel_hdmi_frl_dfm_regs.h

-- 
2.50.1