Intel-XE Archive on lore.kernel.org
 help / color / mirror / Atom feed
From: sashiko-bot@kernel.org
To: "Nareshkumar Gollakoti" <naresh.kumar.g@intel.com>
Cc: intel-xe@lists.freedesktop.org
Subject: Re: [PATCH v2 3/7] drm/xe/guc: Print register addresses in capture snapshot output
Date: Mon, 24 Aug 2026 19:11:23 +0000	[thread overview]
Message-ID: <20260824191124.468641F000E9@smtp.kernel.org> (raw)
In-Reply-To: <20260824184356.1960708-4-naresh.kumar.g@intel.com>

Thank you for your contribution! Sashiko AI review found 2 potential issue(s) to consider:
- [Medium] Incorrect register address calculation for 64-bit registers
- [Low] Format string type mismatch for size_t
--

--- Patch [3]: [PATCH v2 3/7] drm/xe/guc: Print register addresses in capture snapshot output ---
commit baf33cc78a6f2c33ba405aaad2eb334575f207ed
Author: Nareshkumar Gollakoti <naresh.kumar.g@intel.com>

drm/xe/guc: Print register addresses in capture snapshot output
    
This commit modifies the GuC capture snapshot output to include register
offsets alongside their names for both 32-bit and 64-bit registers.

> diff --git a/drivers/gpu/drm/xe/xe_guc_capture.c b/drivers/gpu/drm/xe/xe_guc_capture.c
> index 82df19b304e17..324f25af3b0d0 100644
> --- a/drivers/gpu/drm/xe/xe_guc_capture.c
> +++ b/drivers/gpu/drm/xe/xe_guc_capture.c
> @@ -1774,7 +1774,9 @@ snapshot_print_by_list_order(struct xe_hw_engine_snapshot *snapshot, struct drm_
>  			XE_WARN_ON(!low32_ready);
>  			low32_ready = false;
>  
> -			drm_printf(p, "\t%s: 0x%016llx\n", reg_desc->regname, value_qw);
> +			drm_printf(p, "\t%s (0x%lx): 0x%016llx\n", reg_desc->regname,
> +				   reg_desc->reg.addr - sizeof(u32),
> +				   value_qw);

[Severity: Medium]
Does this correctly calculate the base address for all 64-bit registers?

In the Intel Xe engine MMIO layout, the upper and lower 32-bit registers are
not always exactly 4 bytes apart.

For example, RING_ACTHD (lower 32-bit) is located at offset 0x74, while
RING_ACTHD_UDW (upper 32-bit) is at 0x5c. RING_BBADDR is at 0x140 and
RING_BBADDR_UDW is at 0x168.

By subtracting 4 from 0x5c, the output would incorrectly print 0x58 for ACTHD,
which is actually the address of RING_HWSTAM.

[Severity: Low]
Will this format string trigger a compiler warning on 32-bit platforms?

The expression reg_desc->reg.addr - sizeof(u32) subtracts a size_t from a u32,
promoting the result to size_t. The format string uses %lx, which expects an
unsigned long.

On 32-bit platforms (where the driver can be compile-tested), size_t is
typically unsigned int. Passing an unsigned int to %lx triggers a -Wformat
compiler warning, which could break builds using -Werror.

Should this use %zx for size_t, or explicitly cast the result to u32 and
use %x?

>  			break;
>  		}

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260824184356.1960708-1-naresh.kumar.g@intel.com?part=3

  reply	other threads:[~2026-08-24 19:11 UTC|newest]

Thread overview: 14+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-08-24 18:43 [PATCH v2 0/7] drm/xe: Capture additional HW register state in devcoredump Nareshkumar Gollakoti
2026-08-24 18:43 ` [PATCH v2 1/7] drm/xe/devcoredump: Capture GT fuse registers " Nareshkumar Gollakoti
2026-08-24 18:57   ` sashiko-bot
2026-08-24 18:43 ` [PATCH v2 2/7] drm/xe/devcoredump: Add GuC register snapshot to devcoredump Nareshkumar Gollakoti
2026-08-24 18:43 ` [PATCH v2 3/7] drm/xe/guc: Print register addresses in capture snapshot output Nareshkumar Gollakoti
2026-08-24 19:11   ` sashiko-bot [this message]
2026-08-24 18:43 ` [PATCH v2 4/7] drm/xe: dump GAM page fault report registers in devcoredump Nareshkumar Gollakoti
2026-08-24 18:43 ` [PATCH v2 5/7] drm/xe/guc: add TDL, SLICE gfx registers to capture list Nareshkumar Gollakoti
2026-08-24 18:43 ` [PATCH v2 6/7] drm/xe: capture L3 node status registers in devcoredump Nareshkumar Gollakoti
2026-08-24 18:43 ` [PATCH v2 7/7] drm/xe/guc: capture additional engine state registers Nareshkumar Gollakoti
2026-08-24 19:35   ` sashiko-bot
2026-08-24 23:50 ` ✓ CI.KUnit: success for drm/xe: Capture additional HW register state in devcoredump (rev2) Patchwork
2026-08-25  0:40 ` ✓ Xe.CI.BAT: " Patchwork
2026-08-25  5:10 ` ✗ Xe.CI.FULL: failure " Patchwork

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=20260824191124.468641F000E9@smtp.kernel.org \
    --to=sashiko-bot@kernel.org \
    --cc=intel-xe@lists.freedesktop.org \
    --cc=naresh.kumar.g@intel.com \
    --cc=sashiko-reviews@lists.linux.dev \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox