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From: sashiko-bot@kernel.org
To: "Animesh Manna" <animesh.manna@intel.com>
Cc: intel-xe@lists.freedesktop.org, intel-gfx@lists.freedesktop.org
Subject: Re: [PATCH v5 12/15] drm/i915/alpm: Replace is_edp() with alpm_is_possible()
Date: Tue, 25 Aug 2026 06:43:00 +0000	[thread overview]
Message-ID: <20260825064301.685871F000E9@smtp.kernel.org> (raw)
In-Reply-To: <20260825054536.3455704-13-animesh.manna@intel.com>

Thank you for your contribution! Sashiko AI review found 2 potential issue(s) to consider:
- [High] Flawed logical OR (||) for LTTPR ALPM capabilities and incomplete feature integration.
- [Medium] DPCD capability registers are evaluated without applying capability bitmasks.
--

--- Patch [12]: [PATCH v5 12/15] drm/i915/alpm: Replace is_edp() with alpm_is_possible() ---
commit 7013cc56cbeba3729d838fd8bd915ecee9e1de24
Author: Animesh Manna <animesh.manna@intel.com>

drm/i915/alpm: Replace is_edp() with alpm_is_possible()

Add a separate alpm_is_possible() which will check for both edp and dp.

Cc: Jouni Högander <jouni.hogander@intel.com>

> diff --git a/drivers/gpu/drm/i915/display/intel_alpm.c b/drivers/gpu/drm/i915/display/intel_alpm.c
> index d23f3bdf13399..f3f6f40f96244 100644
> --- a/drivers/gpu/drm/i915/display/intel_alpm.c
> +++ b/drivers/gpu/drm/i915/display/intel_alpm.c

[ ... ]

> @@ -72,6 +72,16 @@ void intel_alpm_init(struct intel_dp *intel_dp)
>  	mutex_init(&intel_dp->alpm.lock);
>  }
>  
> +bool intel_alpm_is_possible(struct intel_dp *intel_dp)
> +{
> +	struct intel_display *display = to_intel_display(intel_dp);
> +
> +	return (DISPLAY_VER(display) >= 12 && intel_dp->alpm_dpcd) ||
> +		(DISPLAY_VER(display) >= 35 &&
> +		intel_dp->lttpr_common_caps[DP_LTTPR_ALPM_CAPABILITIES -
> +					    DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV]);
> +}

[Severity: High]
Should this logical OR (||) be an AND (&&) for LTTPR capabilities? By using
OR, if the LTTPR supports ALPM but the sink does not (or vice versa), this
function will return true.

Could this lead to mismatched configurations? For example, if the LTTPR
supports ALPM but the sink doesn't, intel_alpm_enable_sink() will write
DP_ALPM_MODE_AUX_LESS to the sink's DP_RECEIVER_ALPM_CONFIG register even
though the sink lacks support.

Additionally, downstream functions like intel_alpm_lobf_compute_config()
exclusively check the sink's capability. Does using a logical OR here
effectively render the LTTPR check dead code in those paths?

[Severity: Medium]
Is it safe to evaluate the raw DPCD capability bytes (intel_dp->alpm_dpcd
and lttpr_common_caps) directly as booleans?

Since DPCD 0x02e is a bitfield containing multiple distinct bits (like
DP_ALPM_PM_STATE_2A_SUPPORT), a non-zero value doesn't necessarily mean
basic ALPM capability is supported.

Should this use existing helpers like intel_alpm_aux_wake_supported() or
explicitly apply the DP_ALPM_CAP bitmasks to prevent falsely detecting ALPM
support on reserved bits?

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260825054536.3455704-1-animesh.manna@intel.com?part=12

  reply	other threads:[~2026-08-25  6:43 UTC|newest]

Thread overview: 35+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-08-25  5:45 [PATCH v5 00/15] Enable DP2.1 alpm Animesh Manna
2026-08-25  5:45 ` [PATCH v5 01/15] drm/i915/alpm: Add DPCD definition for DP2.1 ALPM capability Animesh Manna
2026-08-25  7:55   ` Kandpal, Suraj
2026-08-27 10:51     ` Manna, Animesh
2026-08-25  5:45 ` [PATCH v5 02/15] drm/i915/alpm: Move alpm sink capabality readout in separate function Animesh Manna
2026-08-25  6:28   ` sashiko-bot
2026-08-25  7:57   ` Kandpal, Suraj
2026-08-25  5:45 ` [PATCH v5 03/15] drm/i915/alpm: alpm_init() for DP2.1 Animesh Manna
2026-08-25  7:44   ` sashiko-bot
2026-08-25  5:45 ` [PATCH v5 04/15] drm/i915/alpm: Enable debugfs " Animesh Manna
2026-08-25  6:38   ` sashiko-bot
2026-08-25  5:45 ` [PATCH v5 05/15] drm/i915/alpm: Refactor Auxless wake time calculation Animesh Manna
2026-08-25  5:45 ` [PATCH v5 06/15] drm/i915/alpm: Auxless wake time calculation for Xe3p Animesh Manna
2026-08-25  6:30   ` sashiko-bot
2026-08-25  5:45 ` [PATCH v5 07/15] drm/i915/alpm: table based establishment period Animesh Manna
2026-08-25  6:34   ` sashiko-bot
2026-08-25  5:45 ` [PATCH v5 08/15] drm/i915/alpm: Half LFPS cycle calculation Animesh Manna
2026-08-25  6:31   ` sashiko-bot
2026-08-25  5:45 ` [PATCH v5 09/15] drm/i915/alpm: Modify LFPS cycle count for DP ALPM Animesh Manna
2026-08-25  6:33   ` sashiko-bot
2026-08-25  5:45 ` [PATCH v5 10/15] drm/i915/alpm: Program LTTPR count for DP 2.1 ALPM Animesh Manna
2026-08-25  6:32   ` sashiko-bot
2026-08-25  5:45 ` [PATCH v5 11/15] drm/i915/alpm: Enable MAC Transmitting LFPS for LT PHY Animesh Manna
2026-08-25  5:45 ` [PATCH v5 12/15] drm/i915/alpm: Replace is_edp() with alpm_is_possible() Animesh Manna
2026-08-25  6:43   ` sashiko-bot [this message]
2026-08-25  5:45 ` [PATCH v5 13/15] drm/i915/alpm: Introduce has_alpm to decouple from pr/psr2/lobf Animesh Manna
2026-08-25  6:35   ` sashiko-bot
2026-08-25  5:45 ` [PATCH v5 14/15] drm/i915/alpm: Compute and program switch to active latency Animesh Manna
2026-08-25  6:39   ` sashiko-bot
2026-08-25  5:45 ` [PATCH v5 15/15] drm/i915/alpm: Program zero-based LFPS half cycle duration Animesh Manna
2026-08-25  6:40   ` sashiko-bot
2026-08-25  7:59 ` ✗ CI.checkpatch: warning for Enable DP2.1 alpm (rev5) Patchwork
2026-08-25  8:01 ` ✓ CI.KUnit: success " Patchwork
2026-08-25  8:41 ` ✓ Xe.CI.BAT: " Patchwork
2026-08-25 12:23 ` ✓ Xe.CI.FULL: " Patchwork

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