From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 479E3C61DBD for ; Tue, 25 Aug 2026 20:35:13 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id E39EC10EB4A; Tue, 25 Aug 2026 20:35:12 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="erOPhFEt"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.15]) by gabe.freedesktop.org (Postfix) with ESMTPS id C7BCA10EB4A for ; Tue, 25 Aug 2026 20:35:10 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1787690111; x=1819226111; h=from:to:cc:subject:date:message-id:mime-version: content-transfer-encoding; bh=Ppzg3pi4fQl4SnDibUM84MXhhl6fejgMeDKM1+l1TpE=; b=erOPhFEtLNGlB1asbCxBE+RgxQCr2n5d5deSQItyXxDqCp1ieT1gp1WE DXYyhbtGbriOvFKs2LlLck76ePhai+BiTD+WDf98Yl9POu1o5NHxp+Cb0 by83c2V1iSZaGUVfTbFMNA0nkwPnQvW3D0eAk+b2INcRMam02czV0hman 34/nNje5GsxYOpKg5zaNe8i1sE0uA48FzxLC/U2+kylyDbj/TNnqy9MAA SqS5mFYb9JyRJKUsboQQowJRn3S5VHXwHMDDOsHCvbw+gJp2FAjYCKknV XsUFVxtL9uPQcRnM88k2zLrV+chyrwsbYDnVxuulnn/sNdGwLycfwkD2Y A==; X-CSE-ConnectionGUID: eJwTMw2iTWS+4kVF3g/pRA== X-CSE-MsgGUID: 3vcJVOODR/avMejLCyXroQ== X-IronPort-AV: E=McAfee;i="6800,10657,11886"; a="91847495" X-IronPort-AV: E=Sophos;i="6.25,243,1779174000"; d="scan'208";a="91847495" Received: from orviesa007.jf.intel.com ([10.64.159.147]) by orvoesa107.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 25 Aug 2026 13:35:10 -0700 X-CSE-ConnectionGUID: VkH/aaaST7eTNtf307d2aQ== X-CSE-MsgGUID: 2wC42m4XRHyoECBM1DQlEg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.25,243,1779174000"; d="scan'208";a="267415464" Received: from gsse-cloud1.jf.intel.com ([10.54.39.91]) by orviesa007-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 25 Aug 2026 13:35:10 -0700 From: Matthew Brost To: intel-xe@lists.freedesktop.org Cc: Wang Xin , Jia Yao , Jonathan Cavitt Subject: [CI] drm/xe: Disable scheduling early on FD close to avoid CAT error cascade Date: Tue, 25 Aug 2026 13:35:06 -0700 Message-Id: <20260825203506.1791216-1-matthew.brost@intel.com> X-Mailer: git-send-email 2.34.1 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-BeenThere: intel-xe@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel Xe graphics driver List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-xe-bounces@lists.freedesktop.org Sender: "Intel-xe" When an FD is closed with many exec queues, teardown relies on the TDR path to clean up scheduling. However, the TDR handling is serialized (i.e., only one exec queue is processed at a time), which can make it too slow compared to GuC scheduling activity. In this window, GuC may continue to schedule contexts backed by invalid page tables, leading to a cascade of CAT errors and repeated engine resets. This significantly increases recovery time and can degrade system stability. To mitigate this, eagerly disable scheduling by sending a self-message outside of the TDR path. This prevents further scheduling of invalid contexts and avoids the CAT error/reset cascade. This change improves robustness and reduces recovery latency in multiple queue teardown scenarios. Cc: Wang Xin Cc: Jia Yao Signed-off-by: Matthew Brost Tested-by: Jia Yao Reviewed-by: Jonathan Cavitt --- drivers/gpu/drm/xe/xe_guc_exec_queue_types.h | 2 +- drivers/gpu/drm/xe/xe_guc_submit.c | 46 ++++++++++++++++++-- 2 files changed, 43 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/xe/xe_guc_exec_queue_types.h b/drivers/gpu/drm/xe/xe_guc_exec_queue_types.h index d27826b36649..a46cde5ed81f 100644 --- a/drivers/gpu/drm/xe/xe_guc_exec_queue_types.h +++ b/drivers/gpu/drm/xe/xe_guc_exec_queue_types.h @@ -36,7 +36,7 @@ struct xe_guc_exec_queue { * a message needs to sent through the GPU scheduler but memory * allocations are not allowed. */ -#define MAX_STATIC_MSG_TYPE 4 +#define MAX_STATIC_MSG_TYPE 5 struct xe_sched_msg static_msgs[MAX_STATIC_MSG_TYPE]; /** @destroy_async: do final destroy async from this worker */ struct work_struct destroy_async; diff --git a/drivers/gpu/drm/xe/xe_guc_submit.c b/drivers/gpu/drm/xe/xe_guc_submit.c index 99d8c807ff05..33ef884cd316 100644 --- a/drivers/gpu/drm/xe/xe_guc_submit.c +++ b/drivers/gpu/drm/xe/xe_guc_submit.c @@ -1969,12 +1969,23 @@ static void __guc_exec_queue_process_msg_cgp_sync(struct xe_sched_msg *msg, guc_exec_queue_send_cgp_sync(q, 0); } +static void __guc_exec_queue_process_msg_kill(struct xe_sched_msg *msg, + bool bound) +{ + struct xe_exec_queue *q = msg->private_data; + struct xe_exec_queue *primary = xe_exec_queue_multi_queue_primary(q); + + if (exec_queue_enabled(primary) && bound) + disable_scheduling(primary, true); +} + #define CLEANUP 1 /* Non-zero values to catch uninitialized msg */ #define SET_SCHED_PROPS 2 #define SUSPEND 3 #define RESUME 4 #define SET_MULTI_QUEUE_PRIORITY 5 #define CGP_SYNC_MSG 6 +#define KILL 7 #define OPCODE_MASK 0xf #define MSG_LOCKED BIT(8) #define MSG_HEAD BIT(9) @@ -2008,6 +2019,9 @@ static void guc_exec_queue_process_msg(struct xe_sched_msg *msg) case CGP_SYNC_MSG: __guc_exec_queue_process_msg_cgp_sync(msg, bound); break; + case KILL: + __guc_exec_queue_process_msg_kill(msg, bound); + break; default: XE_WARN_ON("Unknown message type"); } @@ -2130,11 +2144,39 @@ static int guc_exec_queue_init(struct xe_exec_queue *q) return err; } +static bool guc_exec_queue_try_add_msg(struct xe_exec_queue *q, + struct xe_sched_msg *msg, + u32 opcode); + +#define STATIC_MSG_CLEANUP 0 +#define STATIC_MSG_SUSPEND 1 +#define STATIC_MSG_RESUME 2 +#define STATIC_MSG_CGP_SYNC 3 +#define STATIC_MSG_KILL 4 static void guc_exec_queue_kill(struct xe_exec_queue *q) { + struct xe_sched_msg *msg = q->guc->static_msgs + STATIC_MSG_KILL; + trace_xe_exec_queue_kill(q); set_exec_queue_killed(q); __suspend_fence_signal(q); + + /* + * We eagerly send a message to ourselves to disable scheduling, as the + * TDR is serialized (i.e., only one exec queue is processed at a time). + * If an FD is closed with many exec queues, the TDR can be slower than + * the GuC scheduling contexts with invalid page tables, creating a + * cascade of CAT errors and engine resets, which is quite slow. Avoid + * this by immediately disabling scheduling outside of the TDR. + */ + if (kref_read(&q->refcount) && !exec_queue_wedged(q)) { + struct xe_gpu_scheduler *sched = &q->guc->sched; + + xe_sched_msg_lock(sched); + guc_exec_queue_try_add_msg(q, msg, KILL); + xe_sched_msg_unlock(sched); + } + xe_guc_exec_queue_trigger_cleanup(q); } @@ -2187,10 +2229,6 @@ static bool guc_exec_queue_try_add_msg(struct xe_exec_queue *q, return true; } -#define STATIC_MSG_CLEANUP 0 -#define STATIC_MSG_SUSPEND 1 -#define STATIC_MSG_RESUME 2 -#define STATIC_MSG_CGP_SYNC 3 static void guc_exec_queue_destroy(struct xe_exec_queue *q) { struct xe_sched_msg *msg = q->guc->static_msgs + STATIC_MSG_CLEANUP; -- 2.34.1