From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 76661C61DB9 for ; Fri, 28 Aug 2026 19:10:22 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 27D1610E43B; Fri, 28 Aug 2026 19:10:22 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="DiUnO5UF"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.14]) by gabe.freedesktop.org (Postfix) with ESMTPS id 32C6A10E087; Fri, 28 Aug 2026 19:10:14 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1787944214; x=1819480214; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=lbciGqLkB1O3QedGWAeYWZV/BI57nLrFiFf8SWNQ7NI=; b=DiUnO5UFHYaAO8uJmRYkUSwaQW2JF9S35chB1EMTLsX0ajNgkrQ5JeRi SHXOU7Tnwpo2cAgJ8GAsYABEltyXWkUMTtAiQjltNCdoM2wHKA+PTRSDK /mkD9CZhyqKkcev7xBbxB46PWzwhxjkIyIQNFLZ5GBn8+s1sf1jXmqxGg dQfJFbnDPPLlzx5dwpy6JJgEISOgIMD1WiubrtBGYLdewrg3TNg8ELvF0 bHDMiyTE/4pZPQu2ZEsVCrypJCdQJwN5iumUDBHHtC9Y6fTR9ppEqBXem K5tYiRO3INirUYgGAVh3f3JaM87M3THVXkYJronFIIjUUhi6zLm4gBWlg w==; X-CSE-ConnectionGUID: 7Oe43eYdRg2+lvFiBKDcyg== X-CSE-MsgGUID: HXtglxMhSbCeNpA2LMMOqg== X-IronPort-AV: E=McAfee;i="6800,10657,11889"; a="92324719" X-IronPort-AV: E=Sophos;i="6.25,249,1779174000"; d="scan'208";a="92324719" Received: from orviesa003.jf.intel.com ([10.64.159.143]) by orvoesa106.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 28 Aug 2026 12:10:14 -0700 X-CSE-ConnectionGUID: pMV52z1tQm6mSmDGWGV5uQ== X-CSE-MsgGUID: eLZ5pcHMTUqbGjX96IA95Q== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.25,249,1779174000"; d="scan'208";a="271758116" Received: from dev-417.igk.intel.com ([10.91.214.181]) by orviesa003.jf.intel.com with ESMTP; 28 Aug 2026 12:10:13 -0700 From: =?UTF-8?q?Micha=C5=82=20Grzelak?= To: intel-gfx@lists.freedesktop.org, intel-xe@lists.freedesktop.org Cc: Jani Nikula , =?UTF-8?q?Micha=C5=82=20Grzelak?= Subject: [PATCH v5 2/2] drm/xe/pcode: match argument naming with PCODE_DATAx Date: Fri, 28 Aug 2026 21:09:56 +0200 Message-ID: <20260828190956.2622350-3-michal.grzelak@intel.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20260828190956.2622350-1-michal.grzelak@intel.com> References: <20260828190956.2622350-1-michal.grzelak@intel.com> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Organization: Intel Technology Poland sp. z o.o. - ul. Slowackiego 173, 80-298 Gdansk - KRS 101882 - NIP 957-07-52-316 Content-Transfer-Encoding: 8bit X-BeenThere: intel-xe@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel Xe graphics driver List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-xe-bounces@lists.freedesktop.org Sender: "Intel-xe" Variable naming of val and val1 should match register macro naming. For xe, register macro naming of PCODE_DATA0 and PCODE_DATA1 is already synced with register name. Nevertheless there are still functions declaring val and val1. Rename val into val0 in functions declaring val1 in xe. v4->v5 - clean changelog's versioning v3->v4 - split i915 changes from xe (Jani) v2->v3 - resolve conflict from rebase v1->v2 - rebase onto drm-tip (Jani) Bspec: 19978, 19979 Suggested-by: Jani Nikula Signed-off-by: Michał Grzelak --- drivers/gpu/drm/xe/display/xe_display_pcode.c | 4 ++-- drivers/gpu/drm/xe/xe_pcode.c | 4 ++-- drivers/gpu/drm/xe/xe_pcode.h | 2 +- 3 files changed, 5 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/xe/display/xe_display_pcode.c b/drivers/gpu/drm/xe/display/xe_display_pcode.c index f6820ef7e666d..8dc9cbdb18ec0 100644 --- a/drivers/gpu/drm/xe/display/xe_display_pcode.c +++ b/drivers/gpu/drm/xe/display/xe_display_pcode.c @@ -6,12 +6,12 @@ #include "xe_device.h" #include "xe_pcode.h" -static int xe_display_pcode_read(struct drm_device *drm, u32 mbox, u32 *val, u32 *val1) +static int xe_display_pcode_read(struct drm_device *drm, u32 mbox, u32 *val0, u32 *val1) { struct xe_device *xe = to_xe_device(drm); struct xe_tile *tile = xe_device_get_root_tile(xe); - return xe_pcode_read(tile, mbox, val, val1); + return xe_pcode_read(tile, mbox, val0, val1); } static int xe_display_pcode_write_timeout(struct drm_device *drm, u32 mbox, u32 val, int timeout_ms) diff --git a/drivers/gpu/drm/xe/xe_pcode.c b/drivers/gpu/drm/xe/xe_pcode.c index 5f7fc61c9b97c..d502205bb72a3 100644 --- a/drivers/gpu/drm/xe/xe_pcode.c +++ b/drivers/gpu/drm/xe/xe_pcode.c @@ -135,12 +135,12 @@ int xe_pcode_write64_timeout(struct xe_tile *tile, u32 mbox, u32 data0, u32 data return err; } -int xe_pcode_read(struct xe_tile *tile, u32 mbox, u32 *val, u32 *val1) +int xe_pcode_read(struct xe_tile *tile, u32 mbox, u32 *val0, u32 *val1) { int err; mutex_lock(&tile->pcode.lock); - err = pcode_mailbox_rw(tile, mbox, val, val1, 1, true, false); + err = pcode_mailbox_rw(tile, mbox, val0, val1, 1, true, false); mutex_unlock(&tile->pcode.lock); return err; diff --git a/drivers/gpu/drm/xe/xe_pcode.h b/drivers/gpu/drm/xe/xe_pcode.h index 8fb3e4ba13a6e..ba8a1d1b21521 100644 --- a/drivers/gpu/drm/xe/xe_pcode.h +++ b/drivers/gpu/drm/xe/xe_pcode.h @@ -23,7 +23,7 @@ int xe_pcode_probe_early(struct xe_device *xe); int xe_pcode_ready(struct xe_device *xe, bool locked); int xe_pcode_init_min_freq_table(struct xe_tile *tile, u32 min_gt_freq, u32 max_gt_freq); -int xe_pcode_read(struct xe_tile *tile, u32 mbox, u32 *val, u32 *val1); +int xe_pcode_read(struct xe_tile *tile, u32 mbox, u32 *val0, u32 *val1); int xe_pcode_write_timeout(struct xe_tile *tile, u32 mbox, u32 val, int timeout_ms); int xe_pcode_write64_timeout(struct xe_tile *tile, u32 mbox, u32 data0, -- 2.45.2