From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id B45C9C624DA for ; Wed, 2 Sep 2026 08:18:00 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 3C39B10F076; Wed, 2 Sep 2026 08:18:00 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="eOdGz3+J"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.12]) by gabe.freedesktop.org (Postfix) with ESMTPS id 29F3B10F06F; Wed, 2 Sep 2026 08:17:59 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1788337079; x=1819873079; h=from:to:subject:date:message-id:in-reply-to:references: mime-version:content-transfer-encoding; bh=g9coBMH/txDMEwqBelPlzvFBXtkx76A4L7OwTR6Nanc=; b=eOdGz3+JNjVDk2t7OMH/Gjjm64Jxxum1sOmBsTIRZrby5zy/7qd3khcH gVZdtRdnpPFgiBMFIitAk41AKGg0hERPww9uhF4GcGSWoWVcmqOywb5oB kQ4zJ0Oj7VojOVgCTNiX6wOA6Bbz1Mruay26AlJ2IVI1j3ixAm7FP/Xuv sKDDCZ5FXjWAxKo+WAxNM0U6IuOrr3FDScfWTyrgemY5HlOw7zB+sxMXi rxjMkEcjhsvtu0uuPLunGaPnGSkCN7qQVhm9a1PXOpHgDFWIWCFwu7HKD Hjd4mfos+BEHCIlECszvBpENw6/5Nu2YjraGCigID67AMX/3UIupKg0OI Q==; X-CSE-ConnectionGUID: e+kHNeWATf674uijpcFqzQ== X-CSE-MsgGUID: B+bIsaEsRPS3U97zAibYpg== X-IronPort-AV: E=McAfee;i="6800,10657,11893"; a="100299818" X-IronPort-AV: E=Sophos;i="6.25,257,1779174000"; d="scan'208";a="100299818" Received: from fmviesa009.fm.intel.com ([10.60.135.149]) by orvoesa104.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 02 Sep 2026 01:17:59 -0700 X-CSE-ConnectionGUID: kSQpfQFASbCaUpq8Mppysw== X-CSE-MsgGUID: G5GP1LHeTM+MKr/Xplgpow== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.25,257,1779174000"; d="scan'208";a="263193676" Received: from dut-2a59.iind.intel.com ([10.190.239.113]) by fmviesa009.fm.intel.com with ESMTP; 02 Sep 2026 01:17:58 -0700 From: Chaitanya Kumar Borah To: intel-xe@lists.freedesktop.org, intel-gfx@lists.freedesktop.org Subject: [CI 6/9] drm/i915/color: Extract HDR post-CSC LUT programming to helper function Date: Wed, 2 Sep 2026 13:24:14 +0530 Message-ID: <20260902075417.656673-7-chaitanya.kumar.borah@intel.com> X-Mailer: git-send-email 2.50.1 In-Reply-To: <20260902075417.656673-1-chaitanya.kumar.borah@intel.com> References: <20260902075417.656673-1-chaitanya.kumar.borah@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-BeenThere: intel-xe@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel Xe graphics driver List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-xe-bounces@lists.freedesktop.org Sender: "Intel-xe" From: Pranay Samala Move HDR plane post-CSC LUT programming to improve code organization. While at it, remove the segment 0 index register writes as it is not currently programmed. Signed-off-by: Pranay Samala Signed-off-by: Chaitanya Kumar Borah Reviewed-by: Uma Shankar --- drivers/gpu/drm/i915/display/intel_color.c | 35 ++++++++++++---------- 1 file changed, 20 insertions(+), 15 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_color.c b/drivers/gpu/drm/i915/display/intel_color.c index 87ced9f6ff40..36c8688ed28e 100644 --- a/drivers/gpu/drm/i915/display/intel_color.c +++ b/drivers/gpu/drm/i915/display/intel_color.c @@ -3998,25 +3998,17 @@ xelpd_program_plane_pre_csc_lut(struct intel_dsb *dsb, } static void -xelpd_program_plane_post_csc_lut(struct intel_dsb *dsb, - const struct intel_plane_state *plane_state) +xelpd_load_hdr_post_csc_lut(struct intel_display *display, + struct intel_dsb *dsb, + enum pipe pipe, + enum plane_id plane, + const struct drm_color_lut32 *post_csc_lut) { - struct intel_display *display = to_intel_display(plane_state); - const struct drm_plane_state *state = &plane_state->uapi; - enum pipe pipe = to_intel_plane(state->plane)->pipe; - enum plane_id plane = to_intel_plane(state->plane)->id; - const struct drm_color_lut32 *post_csc_lut = plane_state->hw.gamma_lut->data; int i, lut_size = 32; u32 lut_val; - if (!icl_is_hdr_plane(display, plane)) - return; - intel_de_write_dsb(display, dsb, PLANE_POST_CSC_GAMC_INDEX_ENH(pipe, plane, 0), PLANE_PAL_PREC_AUTO_INCREMENT); - /* TODO: Add macro */ - intel_de_write_dsb(display, dsb, PLANE_POST_CSC_GAMC_SEG0_INDEX_ENH(pipe, plane, 0), - PLANE_PAL_PREC_AUTO_INCREMENT); for (i = 0; i < lut_size + 3; i++) { if (post_csc_lut) { @@ -4036,8 +4028,21 @@ xelpd_program_plane_post_csc_lut(struct intel_dsb *dsb, } intel_de_write_dsb(display, dsb, PLANE_POST_CSC_GAMC_INDEX_ENH(pipe, plane, 0), 0); - intel_de_write_dsb(display, dsb, - PLANE_POST_CSC_GAMC_SEG0_INDEX_ENH(pipe, plane, 0), 0); +} + +static void +xelpd_program_plane_post_csc_lut(struct intel_dsb *dsb, + const struct intel_plane_state *plane_state) +{ + struct intel_display *display = to_intel_display(plane_state); + const struct drm_plane_state *state = &plane_state->uapi; + enum pipe pipe = to_intel_plane(state->plane)->pipe; + enum plane_id plane = to_intel_plane(state->plane)->id; + const struct drm_color_lut32 *post_csc_lut = plane_state->hw.gamma_lut ? + plane_state->hw.gamma_lut->data : NULL; + + if (icl_is_hdr_plane(display, plane)) + xelpd_load_hdr_post_csc_lut(display, dsb, pipe, plane, post_csc_lut); } static void -- 2.50.1