From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id A9E12C88E42 for ; Fri, 11 Sep 2026 04:15:13 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 3376E10F2B8; Fri, 11 Sep 2026 04:15:13 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="Nnp03KwP"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.18]) by gabe.freedesktop.org (Postfix) with ESMTPS id 42FB110F4DD; Fri, 11 Sep 2026 04:15:07 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1789100108; x=1820636108; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=aqvNk6h2P/59iWCRkrNX1lINhItQZbDOyI1FWGq2iB8=; b=Nnp03KwPXEQ/SAv8msp5cuCI8rrlxYVjsA22ZXTKVS9l/YyQTo2UaGG6 Y5XEFXY/poUC7gF+4r60sOXqucDjUi7RyJy5wjOdgV/SyWH2BvuHbGstg kIuYc4sSNVVSjKcbfwF2JS6asVc3Dham1MGi4edERwzOMVLTWM5iIbzHP Q+5Vib9DkV3WMwJxE/PiByCjGkkWFEPg9jDoQw9rSfimLAkRpsZG47A7e tKdb6114AEcEOuN0GgyTgrOhP8VnzraIFm07DcsTajZabbISvOmufMI9L Q6yQr7vZX5cVG6EPGVWhuXOejoPXtXqKEuhi8Dfjk9tzXu79Zxe+ICA2/ w==; X-CSE-ConnectionGUID: q9/QkPvWQNWLrEELi2stVA== X-CSE-MsgGUID: GgteoLZSQ96wZFrZ2q7SmQ== X-IronPort-AV: E=McAfee;i="6800,10657,11901"; a="89599956" X-IronPort-AV: E=Sophos;i="6.27,96,1787036400"; d="scan'208";a="89599956" Received: from orviesa003.jf.intel.com ([10.64.159.143]) by orvoesa110.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 10 Sep 2026 21:15:07 -0700 X-CSE-ConnectionGUID: ltLLDWRITAm6VLeQzDtBMA== X-CSE-MsgGUID: oM9Kjy18SrykhMw4dRxkGQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.27,96,1787036400"; d="scan'208";a="275334446" Received: from kandpal-x299-ud4-pro.iind.intel.com ([10.190.239.10]) by orviesa003.jf.intel.com with ESMTP; 10 Sep 2026 21:15:06 -0700 From: Suraj Kandpal To: intel-xe@lists.freedesktop.org, intel-gfx@lists.freedesktop.org Cc: ankit.k.nautiyal@intel.com, arun.r.murthy@intel.com, Suraj Kandpal Subject: [PATCH 05/10] drm/i915/display: Add bits for link_n_extended for DISPLAY >= 14 Date: Fri, 11 Sep 2026 09:44:44 +0530 Message-Id: <20260911041449.3699400-6-suraj.kandpal@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260911041449.3699400-1-suraj.kandpal@intel.com> References: <20260911041449.3699400-1-suraj.kandpal@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-BeenThere: intel-xe@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel Xe graphics driver List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-xe-bounces@lists.freedesktop.org Sender: "Intel-xe" From: Ankit Nautiyal LINK_N register has bits 31:24 for extended link N value used for HDMI2.1 and for an alternate mode of operation of DP TG DDA Add the definition for these extra bits, and make intel_set_m_n() explicitly mask the software link_n value down to the low 24 bits, so that a subsequent change can OR the extended field in on top. For DP the extended field is ignored by hardware, so this has no functional effect on its own. v2: Drop extra link_n_ext member. (Jani) v3: Avoid link_n_ext in set_m_n helper. (Jani) v4: Rebase, and update commit message. v5: Drop the now redundant DISPLAY_VER split, the two masks were identical. Bspec:50488 Signed-off-by: Ankit Nautiyal Signed-off-by: Suraj Kandpal --- drivers/gpu/drm/i915/display/intel_display.c | 18 ++++++++++++++++-- .../gpu/drm/i915/display/intel_display_regs.h | 2 ++ 2 files changed, 18 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c index 951856a1694d..4bacdae7d000 100644 --- a/drivers/gpu/drm/i915/display/intel_display.c +++ b/drivers/gpu/drm/i915/display/intel_display.c @@ -2705,14 +2705,22 @@ void intel_set_m_n(struct intel_display *display, intel_reg_t data_m_reg, intel_reg_t data_n_reg, intel_reg_t link_m_reg, intel_reg_t link_n_reg) { + u32 link_n = m_n->link_n; + intel_de_write(display, data_m_reg, TU_SIZE(m_n->tu) | m_n->data_m); intel_de_write(display, data_n_reg, m_n->data_n); intel_de_write(display, link_m_reg, m_n->link_m); + + if (DISPLAY_VER(display) >= 14) + link_n &= ~PIPE_LINK_N1_EXTENDED_MASK; + else + link_n &= DATA_LINK_M_N_MASK; + /* * On BDW+ writing LINK_N arms the double buffered update * of all the M/N registers, so it must be written last. */ - intel_de_write(display, link_n_reg, m_n->link_n); + intel_de_write(display, link_n_reg, link_n); } bool intel_cpu_transcoder_has_m2_n2(struct intel_display *display, @@ -3469,7 +3477,13 @@ void intel_get_m_n(struct intel_display *display, intel_reg_t link_m_reg, intel_reg_t link_n_reg) { m_n->link_m = intel_de_read(display, link_m_reg) & DATA_LINK_M_N_MASK; - m_n->link_n = intel_de_read(display, link_n_reg) & DATA_LINK_M_N_MASK; + m_n->link_n = intel_de_read(display, link_n_reg); + + if (DISPLAY_VER(display) >= 14) + m_n->link_n &= ~PIPE_LINK_N1_EXTENDED_MASK; + else + m_n->link_n &= DATA_LINK_M_N_MASK; + m_n->data_m = intel_de_read(display, data_m_reg) & DATA_LINK_M_N_MASK; m_n->data_n = intel_de_read(display, data_n_reg) & DATA_LINK_M_N_MASK; m_n->tu = REG_FIELD_GET(TU_SIZE_MASK, intel_de_read(display, data_m_reg)) + 1; diff --git a/drivers/gpu/drm/i915/display/intel_display_regs.h b/drivers/gpu/drm/i915/display/intel_display_regs.h index 8251ec15190b..57f388c958b4 100644 --- a/drivers/gpu/drm/i915/display/intel_display_regs.h +++ b/drivers/gpu/drm/i915/display/intel_display_regs.h @@ -1190,6 +1190,8 @@ #define _PIPEA_LINK_N1 0x60044 #define _PIPEB_LINK_N1 0x61044 +#define PIPE_LINK_N1_EXTENDED_MASK REG_GENMASK(31, 24) +#define PIPE_LINK_N1_EXTENDED(val) REG_FIELD_PREP(PIPE_LINK_N1_EXTENDED_MASK, (val)) #define PIPE_LINK_N1(dev_priv, tran) _MMIO_TRANS2(dev_priv, tran, _PIPEA_LINK_N1) #define _PIPEA_LINK_M2 0x60048 -- 2.34.1