From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id C4A25C88E77 for ; Tue, 15 Sep 2026 17:03:46 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 754AA10F230; Tue, 15 Sep 2026 17:03:46 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="lUCE+cYq"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.6]) by gabe.freedesktop.org (Postfix) with ESMTPS id 9F14310F1F2; Tue, 15 Sep 2026 17:03:44 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1789491825; x=1821027825; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=1XLDEWWaYHjC/eZ+kHg0RMR2t8aU2npou1jlhCgycSk=; b=lUCE+cYqCnQc2OL8zi7ab6qLfJH6AX2Fpoo9NemrGX2dxpJYUBb5XMvZ ExAUD3rUrLVK5VXEG1kx9JKqn2vMBWtCk1xAnQ9NXXyV4HfipFHhFkzsk Q+1Ieo/+8NDvUs4lLitFQ2rsh1hD+k0L1mwG860cXCj200iMqWS+CX7Z6 CkQ6kB8ia2D0Ea5MSdwKgivuOAID6GoCbs3BXNC5GGZmQS3mBI4q6CEzd JTP02Nk7SQw5RyahDn78/q1Q4fQ075olfDsMFtOFDXMkuFklpTDu68uEM XvXYY5L82oVa/ho+MmdRWDic8Fm6J08SuwRv+zjuR4J6+d76fsvKVkP9b g==; X-CSE-ConnectionGUID: /Qhj1syGT3yvTwmePb0vIA== X-CSE-MsgGUID: J84AISK0R2a54dKF36HSfA== X-IronPort-AV: E=McAfee;i="6800,10657,11905"; a="371886" X-IronPort-AV: E=Sophos;i="6.27,103,1787036400"; d="scan'208";a="371886" Received: from fmviesa008.fm.intel.com ([10.60.135.148]) by fmvoesa116.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 15 Sep 2026 10:03:44 -0700 X-CSE-ConnectionGUID: hTWJ6GP2SdCnu0XS8SN4pg== X-CSE-MsgGUID: 5X3x7wV2R0aZW+vvHVgZqw== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.27,103,1787036400"; d="scan'208";a="270443908" Received: from srr4-3-linux-103-aknautiy.iind.intel.com ([10.223.34.160]) by fmviesa008-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 15 Sep 2026 10:03:42 -0700 From: Ankit Nautiyal To: intel-gfx@lists.freedesktop.org, intel-xe@lists.freedesktop.org Cc: ville.syrjala@linux.intel.com, arun.r.murthy@intel.com, jani.nikula@linux.intel.com, suraj.kandpal@intel.com, Ankit Nautiyal Subject: [PATCH v7 07/14] drm/i915/dip_regs: Add register definitions for common SDP Transmission Line Date: Tue, 15 Sep 2026 22:16:48 +0530 Message-ID: <20260915164657.3429075-8-ankit.k.nautiyal@intel.com> X-Mailer: git-send-email 2.50.1 In-Reply-To: <20260915164657.3429075-1-ankit.k.nautiyal@intel.com> References: <20260915164657.3429075-1-ankit.k.nautiyal@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-BeenThere: intel-xe@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel Xe graphics driver List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-xe-bounces@lists.freedesktop.org Sender: "Intel-xe" From: Arun R Murthy Add registers definitions for common SDP transmission line CMN_SDP_TL and CMN_SDP_TL_STGR_CTL. v2: Move all registers to intel_dip_regs.h (Ankit) Bspec: 74384 Signed-off-by: Arun R Murthy Signed-off-by: Ankit Nautiyal Reviewed-by: Suraj Kandpal --- drivers/gpu/drm/i915/display/intel_dip_regs.h | 20 +++++++++++++++++++ 1 file changed, 20 insertions(+) diff --git a/drivers/gpu/drm/i915/display/intel_dip_regs.h b/drivers/gpu/drm/i915/display/intel_dip_regs.h index c4e1dab1ea46..d7e40a613913 100644 --- a/drivers/gpu/drm/i915/display/intel_dip_regs.h +++ b/drivers/gpu/drm/i915/display/intel_dip_regs.h @@ -15,4 +15,24 @@ #define EMP_AS_SDP_DB_TL(db_transmit_line) REG_FIELD_PREP(EMP_AS_SDP_DB_TL_MASK, \ (db_transmit_line)) +/* COMMON SDP TRANSMISSION LINE */ +#define _CMN_SDP_TL_A 0x6020c +#define CMN_SDP_TL(display, trans) _MMIO_TRANS2(display, (trans), _CMN_SDP_TL_A) +#define TRANSMISSION_LINE_ENABLE REG_BIT(31) +#define BASE_TRANSMISSION_LINE_MASK REG_GENMASK(12, 0) +#define BASE_TRANSMISSION_LINE(x) REG_FIELD_PREP(BASE_TRANSMISSION_LINE_MASK, x) + +#define _CMN_SDP_TL_STGR_CTL_A 0x60214 +#define CMN_SDP_TL_STGR_CTL(display, trans) _MMIO_TRANS2(display, (trans), \ + _CMN_SDP_TL_STGR_CTL_A) +#define VSC_EXT_STAGGER_MASK REG_GENMASK(11, 8) +#define VSC_EXT_STAGGER(x) REG_FIELD_PREP(VSC_EXT_STAGGER_MASK, x) +#define VSC_EXT_STAGGER_DEFAULT 0x2 +#define PPS_STAGGER_MASK REG_GENMASK(7, 4) +#define PPS_STAGGER(x) REG_FIELD_PREP(PPS_STAGGER_MASK, x) +#define PPS_STAGGER_DEFAULT 0x1 +#define GMP_STAGGER_MASK REG_GENMASK(3, 0) +#define GMP_STAGGER(x) REG_FIELD_PREP(GMP_STAGGER_MASK, x) +#define GMP_STAGGER_DEFAULT 0x0 + #endif /* __INTEL_DIP_REGS_H__ */ -- 2.50.1