From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id D2DDAC982DF for ; Fri, 18 Sep 2026 13:18:32 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 64BD810F3B6; Fri, 18 Sep 2026 13:18:32 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="NcMLDFJv"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.18]) by gabe.freedesktop.org (Postfix) with ESMTPS id 3E10D10F3A3 for ; Fri, 18 Sep 2026 13:18:07 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1789737487; x=1821273487; h=from:to:subject:date:message-id:in-reply-to:references: mime-version:content-transfer-encoding; bh=RbkzW5lz5UdPS267NCAudG2fRXXNske2DKwPw+afHX0=; b=NcMLDFJvSNUfKTx63uhTNGBYPayuqztnlkyA9vL5drfmfuj/0FHe6yZw GhRUo44rlFWRQ2FAxL16VIu6pTDuAuMHZ9yYt/JRr0bFc4AXEmGMlq9Og AQee2PW0DKR+iOvho2qiSSz+qB3JlGJF86WHm3lQEG7Jz91EMDUDKUgwY Zr3It3R+ionWfxR07EMdCBoW+3f0JmakSVNCvMtSiEY9fFoPfaCDuVXJB tYM0PKhchMmr+APBh9tEb7s5rG8Aa71bLsynjADNCUXyizjbp8BldWYPX FBh1OgkxUSVW6OOKpW/GDGreXXL/HjdsLb5TLONzn0v76iVpwxtw8mPig Q==; X-CSE-ConnectionGUID: zDQnWmujS9K2VWEvKCPikg== X-CSE-MsgGUID: Gq25q6d/R4S1+HtgLqlvHA== X-IronPort-AV: E=McAfee;i="6800,10657,11908"; a="89378270" X-IronPort-AV: E=Sophos;i="6.27,109,1787036400"; d="scan'208";a="89378270" Received: from fmviesa006.fm.intel.com ([10.60.135.146]) by fmvoesa112.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 18 Sep 2026 06:18:03 -0700 X-CSE-ConnectionGUID: GeYlD5VqTZGXr8Ue0h/uDw== X-CSE-MsgGUID: I6nsKYa4TyWULgurLas1Fw== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.27,109,1787036400"; d="scan'208";a="270095348" Received: from mjruhl-vm.amr.corp.intel.com ([10.11.186.166]) by fmviesa006-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 18 Sep 2026 06:18:02 -0700 From: "Michael J. Ruhl" To: platform-driver-x86@vger.kernel.org, intel-xe@lists.freedesktop.org, hansg@kernel.org, ilpo.jarvinen@linux.intel.com, matthew.brost@intel.com, rodrigo.vivi@intel.com, thomas.hellstrom@linux.intel.com, airlied@gmail.com, simona@ffwll.ch, david.e.box@linux.intel.com, anoop.c.vijay@intel.com, badal.nilawar@intel.com, matthew.d.roper@intel.com, james.ausmus@intel.com, karthik.poosa@intel.com Subject: [PATCH v10 14/20] drm/xe/vsec: Support Crescent Island PMT Date: Fri, 18 Sep 2026 06:18:05 -0700 Message-ID: <20260918131751.2408883-36-michael.j.ruhl@intel.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260918131751.2408883-22-michael.j.ruhl@intel.com> References: <20260918131751.2408883-22-michael.j.ruhl@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-BeenThere: intel-xe@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel Xe graphics driver List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-xe-bounces@lists.freedesktop.org Sender: "Intel-xe" Crescent Island (CRI) supports PMT telemetry and crashlog. Add Crescent Island (CRI) discovery structure (DVSEC) information to allow for Xe registration. Reviewed-by: Rodrigo Vivi Signed-off-by: Michael J. Ruhl --- drivers/gpu/drm/xe/regs/xe_pmt.h | 8 +++-- drivers/gpu/drm/xe/xe_vsec.c | 51 +++++++++++++++++++++++++++++--- 2 files changed, 53 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/drm/xe/regs/xe_pmt.h b/drivers/gpu/drm/xe/regs/xe_pmt.h index a62ab05c6b4c..2f6658395587 100644 --- a/drivers/gpu/drm/xe/regs/xe_pmt.h +++ b/drivers/gpu/drm/xe/regs/xe_pmt.h @@ -17,8 +17,12 @@ #define PUNIT_VERSION_OFFSET 0xA0 -#define BMG_TELEMETRY_BASE_OFFSET 0xE0000 -#define BMG_TELEMETRY_OFFSET (SOC_BASE + BMG_TELEMETRY_BASE_OFFSET) +#define XE_PMT_BASE_OFFSET 0xE0000 + +#define BMG_TELEMETRY_OFFSET (SOC_BASE + XE_PMT_BASE_OFFSET) + +/* for CRI discovery and telemetry are in an indexed window */ +#define CRI_PMT_OFFSET (SOC_BASE + XE_PMT_BASE_OFFSET) #define BMG_MODS_RESIDENCY_OFFSET (0x4D0) #define BMG_G2_RESIDENCY_OFFSET (0x530) diff --git a/drivers/gpu/drm/xe/xe_vsec.c b/drivers/gpu/drm/xe/xe_vsec.c index 6f312ca3aa4c..f20c1b5373aa 100644 --- a/drivers/gpu/drm/xe/xe_vsec.c +++ b/drivers/gpu/drm/xe/xe_vsec.c @@ -8,6 +8,7 @@ #include #include #include +#include #include #include @@ -32,12 +33,23 @@ * PMT usage. */ -/* PMT GUID value for BMG devices. NOTE: this is NOT a PCI id */ +/* PMT GUID value for BMG and CRI devices. NOTE: this is NOT a PCI id */ #define BMG_DEVICE_ID 0xE2F8 +#define CRI_DEVICE_ID 0xE2FA + +/* + * sizeof(Crashlog Type1 Version2) = 0x18 (24) bytes + * For BMG and CRI PUNIT and OOBMSMS crashlogs are consecutive. + */ +#define BMG_CRASHLOG_PUNIT_DISC_OFFSET (0x60) +#define BMG_CRASHLOG_OOBMSM_DISC_OFFSET (BMG_CRASHLOG_PUNIT_DISC_OFFSET + 0x18) + +#define CRI_CRASHLOG_PUNIT_DISC_OFFSET (0x80) +#define CRI_CRASHLOG_OOBMSM_DISC_OFFSET (CRI_CRASHLOG_PUNIT_DISC_OFFSET + 0x18) static struct intel_vsec_header bmg_telemetry = { .rev = 1, - .length = 0x10, + .length = SZ_16, .id = VSEC_ID_TELEMETRY, .num_entries = 2, .entry_size = 4, @@ -47,12 +59,12 @@ static struct intel_vsec_header bmg_telemetry = { static struct intel_vsec_header bmg_crashlog = { .rev = 1, - .length = 0x10, + .length = SZ_16, .id = VSEC_ID_CRASHLOG, .num_entries = 2, .entry_size = 6, .tbir = 0, - .offset = BMG_DISCOVERY_OFFSET + 0x60, + .offset = BMG_DISCOVERY_OFFSET + BMG_CRASHLOG_PUNIT_DISC_OFFSET, }; static struct intel_vsec_header *bmg_capabilities[] = { @@ -61,9 +73,36 @@ static struct intel_vsec_header *bmg_capabilities[] = { NULL }; +static struct intel_vsec_header cri_telemetry = { + .rev = 1, + .length = SZ_16, + .id = VSEC_ID_TELEMETRY, + .num_entries = 3, + .entry_size = 4, + .tbir = 0, + .offset = CRI_PMT_OFFSET, +}; + +static struct intel_vsec_header cri_crashlog = { + .rev = 1, + .length = SZ_16, + .id = VSEC_ID_CRASHLOG, + .num_entries = 2, + .entry_size = 6, + .tbir = 0, + .offset = CRI_PMT_OFFSET + CRI_CRASHLOG_PUNIT_DISC_OFFSET, +}; + +static struct intel_vsec_header *cri_capabilities[] = { + &cri_telemetry, + &cri_crashlog, + NULL +}; + enum xe_vsec { XE_VSEC_UNKNOWN = 0, XE_VSEC_BMG, + XE_VSEC_CRI, }; static struct intel_vsec_platform_info xe_vsec_info[] = { @@ -71,6 +110,10 @@ static struct intel_vsec_platform_info xe_vsec_info[] = { .caps = VSEC_CAP_TELEMETRY | VSEC_CAP_CRASHLOG, .headers = bmg_capabilities, }, + [XE_VSEC_CRI] = { + .caps = VSEC_CAP_TELEMETRY | VSEC_CAP_CRASHLOG, + .headers = cri_capabilities, + }, { } }; -- 2.43.0