From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 7F007C9831E for ; Thu, 24 Sep 2026 23:01:53 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 3756D10E767; Thu, 24 Sep 2026 23:01:53 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="fKmaoo9p"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.17]) by gabe.freedesktop.org (Postfix) with ESMTPS id 6C45E10E8C6 for ; Thu, 24 Sep 2026 23:01:23 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1790290884; x=1821826884; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=EFcjNdA1O4F9Bi40HJPxypS+NxB3YL+LsOiTO5QAkZ8=; b=fKmaoo9pWG4tTLvtusePw3KFY9t5CzCd6jDdUy1/CBjmGYkHrJMcI8+/ DdcZSEnEmCWPn4v9jc5/FK/s3LiQyqeR0wpRxZlAngIFdxtGsGqX3zxZi fTbHtIxYxH4Tfq2qYoRciy3VUoauWP4oFO+5d2n7ovW3TH6lAHs9mbQsL 4TclgdIOLry3rMX4YjEO+sS+fIxnshUCfQpu5LB28EOJkZw35W1rpeKLR XCHRKwa30K9iUcfGbyF2LjEUjSnveg1YL+k3ifmbCBEWzH6w+erBDzCx0 JcCFhpYfafC7rx/XO7E6wWp8DPycTUmdqpppL0sOa9izGu+mWUlcOMaAC w==; X-CSE-ConnectionGUID: 7E8VkW5zSmulUROgNcJp5Q== X-CSE-MsgGUID: tQGixnURSZ60mbUsHRXHfg== X-IronPort-AV: E=McAfee;i="6800,10657,11915"; a="90120175" X-IronPort-AV: E=Sophos;i="6.27,121,1787036400"; d="scan'208";a="90120175" Received: from fmviesa009.fm.intel.com ([10.60.135.149]) by orvoesa109.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 24 Sep 2026 16:01:23 -0700 X-CSE-ConnectionGUID: SBjH/Ue4ToykRMTPdVAQjw== X-CSE-MsgGUID: Q9NExF1kTW6Y+hcKMHHJqw== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.27,121,1787036400"; d="scan'208";a="270651612" Received: from dut4435arlh.fm.intel.com ([10.105.8.61]) by fmviesa009-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 24 Sep 2026 16:01:22 -0700 From: Stuart Summers To: Cc: intel-xe@lists.freedesktop.org, rodrigo.vivi@intel.com, matthew.brost@intel.com, umesh.nerlige.ramappa@intel.com, gustavo.sousa@intel.com, matthew.d.roper@intel.com, daniele.ceraolospurio@intel.com, shuicheng.lin@intel.com, Stuart Summers Subject: [PATCH 08/16] drm/xe: Split out configfs data structures Date: Thu, 24 Sep 2026 23:01:27 +0000 Message-ID: <20260924230120.389685-26-stuart.summers@intel.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260924230120.389685-18-stuart.summers@intel.com> References: <20260924230120.389685-18-stuart.summers@intel.com> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-BeenThere: intel-xe@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel Xe graphics driver List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-xe-bounces@lists.freedesktop.org Sender: "Intel-xe" Planning on moving debug specific configfs parameters to their own file in a future patch. In preparation for that change, move the structures in xe_configfs.c to a new _types.h file so we can easily access them in the different configfs files. Doing that separately here instead of combining with the patch that adds the debug file for ease of review. Signed-off-by: Stuart Summers Assisted-by: Copilot:claude-sonnet-4.6,claude-opus-4.7 Reviewed-by: Matt Roper --- drivers/gpu/drm/xe/xe_configfs.c | 42 -------------------- drivers/gpu/drm/xe/xe_configfs.h | 2 +- drivers/gpu/drm/xe/xe_configfs_types.h | 54 ++++++++++++++++++++++++++ 3 files changed, 55 insertions(+), 43 deletions(-) create mode 100644 drivers/gpu/drm/xe/xe_configfs_types.h diff --git a/drivers/gpu/drm/xe/xe_configfs.c b/drivers/gpu/drm/xe/xe_configfs.c index 9e0f5af30b0c..172298713a1b 100644 --- a/drivers/gpu/drm/xe/xe_configfs.c +++ b/drivers/gpu/drm/xe/xe_configfs.c @@ -4,7 +4,6 @@ */ #include -#include #include #include #include @@ -17,10 +16,7 @@ #include "xe_configfs.h" #include "xe_defaults.h" #include "xe_gt_types.h" -#include "xe_hw_engine_types.h" #include "xe_module.h" -#include "xe_pci_types.h" -#include "xe_sriov_types.h" /** * DOC: Xe Configfs @@ -275,44 +271,6 @@ * # rmdir /sys/kernel/config/xe/0000:03:00.0/ */ -/* Similar to struct xe_bb, but not tied to HW (yet) */ -struct wa_bb { - u32 *cs; - u32 len; /* in dwords */ -}; - -struct xe_config_group_device { - struct config_group group; - struct config_group sriov; - - /* - * Fields sorted by type (largest first) then name: struct arrays, - * u64, u32/unsigned int, u8, bool, sub-structs last. Within each - * type, entries are sorted alphabetically. - */ - struct xe_config_device { - struct wa_bb ctx_restore_mid_bb[XE_ENGINE_CLASS_MAX]; - struct wa_bb ctx_restore_post_bb[XE_ENGINE_CLASS_MAX]; - u64 engines_allowed; - u64 gt_types_allowed; - u8 survivability_mode; - bool enable_multi_queue; - bool enable_psmi; - bool enable_vram_page_offline; - struct { - unsigned int max_vfs; - bool admin_only_pf; - } sriov; - } config; - - /* protects attributes */ - struct mutex lock; - /* matching descriptor */ - const struct xe_device_desc *desc; - /* tentative SR-IOV mode */ - enum xe_sriov_mode mode; -}; - static const struct xe_config_device device_defaults = { .engines_allowed = U64_MAX, .gt_types_allowed = U64_MAX, diff --git a/drivers/gpu/drm/xe/xe_configfs.h b/drivers/gpu/drm/xe/xe_configfs.h index deae0ebf3c2b..ce10ca87b291 100644 --- a/drivers/gpu/drm/xe/xe_configfs.h +++ b/drivers/gpu/drm/xe/xe_configfs.h @@ -8,7 +8,7 @@ #include #include -#include "xe_hw_engine_types.h" +#include "xe_configfs_types.h" struct pci_dev; diff --git a/drivers/gpu/drm/xe/xe_configfs_types.h b/drivers/gpu/drm/xe/xe_configfs_types.h new file mode 100644 index 000000000000..36c48cb4c8b8 --- /dev/null +++ b/drivers/gpu/drm/xe/xe_configfs_types.h @@ -0,0 +1,54 @@ +/* SPDX-License-Identifier: MIT */ +/* + * Copyright © 2026 Intel Corporation + */ +#ifndef _XE_CONFIGFS_TYPES_H_ +#define _XE_CONFIGFS_TYPES_H_ + +#include +#include +#include + +#include "xe_hw_engine_types.h" +#include "xe_pci_types.h" +#include "xe_sriov_types.h" + +/* Similar to struct xe_bb, but not tied to HW (yet) */ +struct wa_bb { + u32 *cs; + u32 len; /* in dwords */ +}; + +struct xe_config_group_device { + struct config_group group; + struct config_group sriov; + + /* + * Fields sorted by type (largest first) then name: struct arrays, + * u64, u32/unsigned int, u8, bool, sub-structs last. Within each + * type, entries are sorted alphabetically. + */ + struct xe_config_device { + struct wa_bb ctx_restore_mid_bb[XE_ENGINE_CLASS_MAX]; + struct wa_bb ctx_restore_post_bb[XE_ENGINE_CLASS_MAX]; + u64 engines_allowed; + u64 gt_types_allowed; + u8 survivability_mode; + bool enable_multi_queue; + bool enable_psmi; + bool enable_vram_page_offline; + struct { + unsigned int max_vfs; + bool admin_only_pf; + } sriov; + } config; + + /* protects attributes */ + struct mutex lock; + /* matching descriptor */ + const struct xe_device_desc *desc; + /* tentative SR-IOV mode */ + enum xe_sriov_mode mode; +}; + +#endif /* _XE_CONFIGFS_TYPES_H_ */ -- 2.43.0