From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 01F1DCA5FA1 for ; Tue, 29 Sep 2026 09:45:04 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id AE0AF10E9C7; Tue, 29 Sep 2026 09:45:04 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="LpPoMfcZ"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.17]) by gabe.freedesktop.org (Postfix) with ESMTPS id 18DCC10E9C7; Tue, 29 Sep 2026 09:45:03 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1790675103; x=1822211103; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=dHVrYUivxUotk9cuCCZ9jTUBL9qD5bAULxGWceTv/Q8=; b=LpPoMfcZF/pRmuWOJk/A9/EGa0rew3A8HFwJM2ac9zEuqmwvAbnKG2LT TTkw0bNkB80W0Ym8Lk5rN4Euwpk5tNvM0u/JN2OgVWFfdDiNvIBxgwFup xTCA2clbHCeb2sEn+0z52o6wrH8aqV3TYaBHmOU7XTVIuNM+ELkU0ngL/ cESpVSivbBa7uzEudHFx/PV95c7ZcVjsetCPoAfrbW6WM1ssSAVSnSwgi 1rW0RuxR9v025qFFM0Cvgd80mAVXrTWlyI0RMngt6PLSYhCpJJYWTZxdT mb0HXQlelVDTwo59vfJAmvl4fQJboJ9/v6kGDXovatcQiv6lFAoRvjhD6 A==; X-CSE-ConnectionGUID: SaMcZTvfRLyBlmaVT9Fp9Q== X-CSE-MsgGUID: hksk+R7lSsaypec7S775QQ== X-IronPort-AV: E=McAfee;i="6800,10657,11919"; a="91250054" X-IronPort-AV: E=Sophos;i="6.27,130,1787036400"; d="scan'208";a="91250054" Received: from fmviesa005.fm.intel.com ([10.60.135.145]) by fmvoesa111.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 29 Sep 2026 02:44:54 -0700 X-CSE-ConnectionGUID: fGM2DyLTR12tHn0OOxl8Ug== X-CSE-MsgGUID: 2qKzAb27R3G/V1t+CDWrqg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.27,130,1787036400"; d="scan'208";a="283414964" Received: from mjarzebo-mobl1.ger.corp.intel.com (HELO jhogande-mobl3.intel.com) ([10.245.246.120]) by fmviesa005-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 29 Sep 2026 02:44:52 -0700 From: =?UTF-8?q?Jouni=20H=C3=B6gander?= To: intel-gfx@lists.freedesktop.org, intel-xe@lists.freedesktop.org Cc: =?UTF-8?q?Jouni=20H=C3=B6gander?= , stable@vger.kernel.org Subject: [PATCH 2/8] drm/i915/display: Add enabled pipe planes into state for selective fetch Date: Tue, 29 Sep 2026 12:44:28 +0300 Message-ID: <20260929094434.77129-3-jouni.hogander@intel.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260929094434.77129-1-jouni.hogander@intel.com> References: <20260929094434.77129-1-jouni.hogander@intel.com> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Organization: Intel Finland Oy - BIC 0357606-4 - Westendinkatu 7, 02160 Espoo Content-Transfer-Encoding: 8bit X-BeenThere: intel-xe@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel Xe graphics driver List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-xe-bounces@lists.freedesktop.org Sender: "Intel-xe" Selective fetch support for biplanar formats relies on linking of UV and the Y planes. Planes that are not part of the atomic state are pulled in by the drm_atomic_add_affected_planes. If the UV plane is added into the state by drm_atomic_add_affected_planes in the selective fetch calculation, the linking isn't done anymore and the Y plane is left disabled. Fix this by adding affected planes already in intel_add_affected_planes if selective fetch is enabled. Remove redundant drm_atomic_add_affected_planes from intel_psr2_sel_fetch_update and redundant check for plane selective fetch support that is not needed as all planes are already in atomic state on first loop iterating them. Also switch to intel_atomic_get_new_plane_state for linked plane new plane state. Fixes: 3809991ff5f4 ("drm/i915/display: Add initial selective fetch support for biplanar formats") Cc: # v5.17+ Signed-off-by: Jouni Högander --- drivers/gpu/drm/i915/display/intel_plane.c | 10 +++++++++ drivers/gpu/drm/i915/display/intel_psr.c | 25 +++++++--------------- 2 files changed, 18 insertions(+), 17 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_plane.c b/drivers/gpu/drm/i915/display/intel_plane.c index f908eabe604bb..d23de0f34e4b6 100644 --- a/drivers/gpu/drm/i915/display/intel_plane.c +++ b/drivers/gpu/drm/i915/display/intel_plane.c @@ -1980,6 +1980,16 @@ static int intel_add_affected_planes(struct intel_atomic_state *state) ret = intel_joiner_add_affected_planes(state, intel_crtc_joined_pipe_mask(crtc_state)); if (ret) return ret; + + /* + * Add affected plane here to ensure UV and Y plane linking is + * in place if UV plane is added as a part of selective update. + */ + if (crtc_state->enable_psr2_sel_fetch) { + ret = intel_plane_add_affected(state, crtc); + if (ret) + return ret; + } } return 0; diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c index f620c44ee4008..a9e9215200015 100644 --- a/drivers/gpu/drm/i915/display/intel_psr.c +++ b/drivers/gpu/drm/i915/display/intel_psr.c @@ -2902,7 +2902,7 @@ int intel_psr2_sel_fetch_update(struct intel_atomic_state *state, .y2 = crtc_state->hw.adjusted_mode.crtc_vdisplay, }; bool full_update = false, su_area_changed; - int i, ret; + int i; /* * Selective fetch is not always usable, for instance it is dropped @@ -3017,19 +3017,15 @@ int intel_psr2_sel_fetch_update(struct intel_atomic_state *state, intel_psr_apply_su_area_workarounds(crtc_state); - ret = drm_atomic_add_affected_planes(&state->base, &crtc->base); - if (ret) - return ret; - do { bool cursor_in_su_area = false; /* * Adjust su area to cover cursor fully as necessary - * (early transport). This needs to be done after - * drm_atomic_add_affected_planes to ensure visible - * cursor is added into affected planes even when - * cursor is not updated by itself. + * (early transport). A visible cursor is in the state + * even when it is not updated by itself as all planes + * of the pipe are added into the state before the plane + * checks when selective fetch is enabled. */ intel_psr2_sel_fetch_et_alignment(state, crtc, &display_area, &cursor_in_su_area); @@ -3080,11 +3076,6 @@ int intel_psr2_sel_fetch_update(struct intel_atomic_state *state, continue; } - if (!psr2_sel_fetch_plane_state_supported(new_plane_state)) { - full_update = true; - break; - } - sel_fetch_area = &new_plane_state->psr2_sel_fetch_area; sel_fetch_area->y1 = inter.y1 - new_plane_state->uapi.dst.y1; sel_fetch_area->y2 = inter.y2 - new_plane_state->uapi.dst.y1; @@ -3098,9 +3089,9 @@ int intel_psr2_sel_fetch_update(struct intel_atomic_state *state, struct intel_plane_state *linked_new_plane_state; struct drm_rect *linked_sel_fetch_area; - linked_new_plane_state = intel_atomic_get_plane_state(state, linked); - if (IS_ERR(linked_new_plane_state)) - return PTR_ERR(linked_new_plane_state); + linked_new_plane_state = intel_atomic_get_new_plane_state(state, linked); + if (!linked_new_plane_state) + return -EINVAL; linked_sel_fetch_area = &linked_new_plane_state->psr2_sel_fetch_area; linked_sel_fetch_area->y1 = sel_fetch_area->y1; -- 2.43.0