From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 3FF0ECA5FA5 for ; Tue, 29 Sep 2026 09:45:08 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id E58DD10EDE5; Tue, 29 Sep 2026 09:45:07 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="WXLme7hQ"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.17]) by gabe.freedesktop.org (Postfix) with ESMTPS id 90A4A10E9C7; Tue, 29 Sep 2026 09:45:03 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1790675104; x=1822211104; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=MVmXUnBjOenICh1yyRgj9f8Knp/0Q36f3RawBrNMaiI=; b=WXLme7hQB6kYvbZrmaWKq2eExOCV07H/wJOPC4/IFymf7vRZ2/yDgHxj U2AbzUL9hKLsvby6vasPz5kLD8t/bZTZVU1aR8BaYkf8sFkQ+xEGChRIi RG9Uhb9L2k9JwAi+dqbUdoLy3GUssMauQG14yXDUiXl0iyyZ6+IEX6QOq uIRM+1J94EeNpGiVGP74ROU7lbObGOaAi3xMSrtH8nZbWolDPlNM0tpnt zaQ2EBkRqUGTJG4j9urfv9AyecG10+oXv8dSnd/RxyU1k0C7Llpc/3BsV ArGepmzyzEQbakg40JGVpNe5vuA1xkfUmJ2Y9vPnaX8ubXac7Kk40xFn1 g==; X-CSE-ConnectionGUID: FZf47C26QIK9Xk9G9rzVtA== X-CSE-MsgGUID: HguNhzY1QzWa4/6+0+o8zQ== X-IronPort-AV: E=McAfee;i="6800,10657,11919"; a="91250061" X-IronPort-AV: E=Sophos;i="6.27,130,1787036400"; d="scan'208";a="91250061" Received: from fmviesa005.fm.intel.com ([10.60.135.145]) by fmvoesa111.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 29 Sep 2026 02:44:56 -0700 X-CSE-ConnectionGUID: OL2yPaEKTOexGlNovH1GxA== X-CSE-MsgGUID: EYypfGSURZu3nRZZvfbneQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.27,130,1787036400"; d="scan'208";a="283414981" Received: from mjarzebo-mobl1.ger.corp.intel.com (HELO jhogande-mobl3.intel.com) ([10.245.246.120]) by fmviesa005-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 29 Sep 2026 02:44:54 -0700 From: =?UTF-8?q?Jouni=20H=C3=B6gander?= To: intel-gfx@lists.freedesktop.org, intel-xe@lists.freedesktop.org Cc: =?UTF-8?q?Jouni=20H=C3=B6gander?= , stable@vger.kernel.org Subject: [PATCH 3/8] drm/i915/psr: Disable linked plane sel fetch as well Date: Tue, 29 Sep 2026 12:44:29 +0300 Message-ID: <20260929094434.77129-4-jouni.hogander@intel.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260929094434.77129-1-jouni.hogander@intel.com> References: <20260929094434.77129-1-jouni.hogander@intel.com> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Organization: Intel Finland Oy - BIC 0357606-4 - Westendinkatu 7, 02160 Espoo Content-Transfer-Encoding: 8bit X-BeenThere: intel-xe@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel Xe graphics driver List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-xe-bounces@lists.freedesktop.org Sender: "Intel-xe" Currently we are not setting linked plane selective area when selective fetch is about to be disabled for the UV plane. Fix this by simplifying the loop by just handling plane selective fetch disable and area setting same way. Also set the update_planes bit based on comparing old and new plane selective fetch area. This way both the plane and its linked Y plane are updated only when their selective fetch area changed. Fixes: a4f477e6ac17 ("drm/i915/psr: Add proper handling for disabling sel fetch for planes") Cc: # v6.8+ Assisted-by: GitHub-Copilot:claude-opus-5 Signed-off-by: Jouni Högander --- drivers/gpu/drm/i915/display/intel_psr.c | 27 ++++++++++++------------ 1 file changed, 13 insertions(+), 14 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c index a9e9215200015..f2ec7b0e0668c 100644 --- a/drivers/gpu/drm/i915/display/intel_psr.c +++ b/drivers/gpu/drm/i915/display/intel_psr.c @@ -3065,21 +3065,14 @@ int intel_psr2_sel_fetch_update(struct intel_atomic_state *state, inter = crtc_state->psr2_su_area; sel_fetch_area = &new_plane_state->psr2_sel_fetch_area; - if (!drm_rect_intersect(&inter, &new_plane_state->uapi.dst)) { - /* - * if plane sel fetch was previously enabled -> - * disable it - */ - if (drm_rect_height(&old_plane_state->psr2_sel_fetch_area) > 0) - crtc_state->update_planes |= BIT(plane->id); - - continue; + if (drm_rect_intersect(&inter, &new_plane_state->uapi.dst)) { + sel_fetch_area->y1 = inter.y1 - new_plane_state->uapi.dst.y1; + sel_fetch_area->y2 = inter.y2 - new_plane_state->uapi.dst.y1; } - sel_fetch_area = &new_plane_state->psr2_sel_fetch_area; - sel_fetch_area->y1 = inter.y1 - new_plane_state->uapi.dst.y1; - sel_fetch_area->y2 = inter.y2 - new_plane_state->uapi.dst.y1; - crtc_state->update_planes |= BIT(plane->id); + if (!drm_rect_equals(&old_plane_state->psr2_sel_fetch_area, + sel_fetch_area)) + crtc_state->update_planes |= BIT(plane->id); /* * Sel_fetch_area is calculated for UV plane. Use @@ -3087,16 +3080,22 @@ int intel_psr2_sel_fetch_update(struct intel_atomic_state *state, */ if (linked) { struct intel_plane_state *linked_new_plane_state; + struct intel_plane_state *linked_old_plane_state; struct drm_rect *linked_sel_fetch_area; linked_new_plane_state = intel_atomic_get_new_plane_state(state, linked); if (!linked_new_plane_state) return -EINVAL; + linked_old_plane_state = intel_atomic_get_old_plane_state(state, linked); + linked_sel_fetch_area = &linked_new_plane_state->psr2_sel_fetch_area; linked_sel_fetch_area->y1 = sel_fetch_area->y1; linked_sel_fetch_area->y2 = sel_fetch_area->y2; - crtc_state->update_planes |= BIT(linked->id); + + if (!drm_rect_equals(&linked_old_plane_state->psr2_sel_fetch_area, + linked_sel_fetch_area)) + crtc_state->update_planes |= BIT(linked->id); } } -- 2.43.0