From: Matthew Brost <matthew.brost@intel.com>
To: intel-xe@lists.freedesktop.org
Subject: [PATCH 2/3] drm/xe: Add xe_migrate_clear_vram
Date: Tue, 29 Sep 2026 11:10:23 -0700 [thread overview]
Message-ID: <20260929181024.2743854-3-matthew.brost@intel.com> (raw)
In-Reply-To: <20260929181024.2743854-1-matthew.brost@intel.com>
Add a clear which takes a device physical address and a page count
rather than a struct ttm_resource, so callers which only know the
physical extent of a VRAM range can zero it.
VRAM is reachable through the migrate identity map, so no page table
updates are required and the batch is just the clear (plus a CCS clear
on platforms which need one).
The upcoming SVM user skips the clear at allocation time and instead
clears only the ranges which are not fully overwritten by a migration.
Assisted-by: Github-Copilot:Claude-opus-5
Signed-off-by: Matthew Brost <matthew.brost@intel.com>
---
drivers/gpu/drm/xe/xe_migrate.c | 89 +++++++++++++++++++++++++++++++++
drivers/gpu/drm/xe/xe_migrate.h | 5 ++
2 files changed, 94 insertions(+)
diff --git a/drivers/gpu/drm/xe/xe_migrate.c b/drivers/gpu/drm/xe/xe_migrate.c
index 0dfc54ba3b8f..04c7cb8aec68 100644
--- a/drivers/gpu/drm/xe/xe_migrate.c
+++ b/drivers/gpu/drm/xe/xe_migrate.c
@@ -2371,6 +2371,95 @@ struct dma_fence *xe_migrate_from_vram(struct xe_migrate *m,
deps, XE_MIGRATE_COPY_TO_SRAM);
}
+/**
+ * xe_migrate_clear_vram() - Clear a VRAM device physical address range
+ * @m: The migration context.
+ * @npages: Number of pages to clear.
+ * @vram_addr: Device physical address of VRAM to clear.
+ * @deps: struct dma_fence representing the dependencies that need to be
+ * signaled before the clear.
+ *
+ * Zero a physically contiguous VRAM range addressed by its device physical
+ * address rather than by a &struct ttm_resource. Used by SVM, which skips the
+ * clear at allocation time and instead clears only the ranges which are not
+ * fully overwritten by a subsequent migration.
+ *
+ * Return: dma fence for the clear to signal completion on success, ERR_PTR on
+ * failure
+ */
+struct dma_fence *xe_migrate_clear_vram(struct xe_migrate *m,
+ unsigned long npages,
+ u64 vram_addr,
+ struct dma_fence *deps)
+{
+ struct xe_gt *gt = m->tile->primary_gt;
+ struct xe_device *xe = gt_to_xe(gt);
+ bool use_usm_batch = xe->info.has_usm;
+ unsigned long len = npages * PAGE_SIZE;
+ u32 flush_flags = 0, batch_size, update_idx;
+ struct dma_fence *fence;
+ struct xe_sched_job *job;
+ struct xe_bb *bb;
+ u64 clear_ofs;
+ int err;
+
+ xe_assert(xe, len <= MAX_PREEMPTDISABLE_TRANSFER);
+
+ batch_size = 1 + emit_clear_cmd_len(gt);
+ if (xe_migrate_needs_ccs_emit(xe))
+ batch_size += EMIT_COPY_CCS_DW;
+
+ bb = xe_bb_new(gt, batch_size, use_usm_batch);
+ if (IS_ERR(bb))
+ return ERR_CAST(bb);
+
+ clear_ofs = xe_migrate_vram_ofs(xe, vram_addr, false);
+
+ bb->cs[bb->len++] = MI_BATCH_BUFFER_END;
+ update_idx = bb->len;
+
+ emit_clear(gt, bb, clear_ofs, len, XE_PAGE_SIZE, true);
+
+ if (xe_migrate_needs_ccs_emit(xe)) {
+ emit_copy_ccs(gt, bb, clear_ofs, true, m->cleared_mem_ofs,
+ false, len);
+ flush_flags |= MI_FLUSH_DW_CCS;
+ }
+
+ job = xe_bb_create_migration_job(m->q, bb,
+ xe_migrate_batch_base(m, use_usm_batch),
+ update_idx);
+ if (IS_ERR(job)) {
+ err = PTR_ERR(job);
+ goto err;
+ }
+
+ xe_sched_job_add_migrate_flush(job, flush_flags);
+
+ if (deps && !dma_fence_is_signaled(deps)) {
+ dma_fence_get(deps);
+ err = drm_sched_job_add_dependency(&job->drm, deps);
+ if (err)
+ dma_fence_wait(deps, false);
+ }
+
+ mutex_lock(&m->job_mutex);
+ fence = xe_migrate_job_push(m, job);
+
+ dma_fence_put(m->fence);
+ m->fence = dma_fence_get(fence);
+ mutex_unlock(&m->job_mutex);
+
+ xe_bb_free(bb, fence);
+
+ return fence;
+
+err:
+ xe_bb_free(bb, NULL);
+
+ return ERR_PTR(err);
+}
+
static void xe_migrate_dma_unmap(struct xe_device *xe,
struct drm_pagemap_addr *pagemap_addr,
int len, int write)
diff --git a/drivers/gpu/drm/xe/xe_migrate.h b/drivers/gpu/drm/xe/xe_migrate.h
index 2e8be10fdb71..fc38204394f6 100644
--- a/drivers/gpu/drm/xe/xe_migrate.h
+++ b/drivers/gpu/drm/xe/xe_migrate.h
@@ -49,6 +49,11 @@ struct dma_fence *xe_migrate_from_vram(struct xe_migrate *m,
struct drm_pagemap_addr *dst_addr,
struct dma_fence *deps);
+struct dma_fence *xe_migrate_clear_vram(struct xe_migrate *m,
+ unsigned long npages,
+ u64 vram_addr,
+ struct dma_fence *deps);
+
struct dma_fence *xe_migrate_copy(struct xe_migrate *m,
struct xe_bo *src_bo,
struct xe_bo *dst_bo,
--
2.34.1
next prev parent reply other threads:[~2026-09-29 18:10 UTC|newest]
Thread overview: 13+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-09-29 18:10 [PATCH 0/3] Elide clear on full SVM copies Matthew Brost
2026-09-29 18:10 ` [PATCH 1/3] drm/xe: Add XE_BO_FLAG_SKIP_CLEAR Matthew Brost
2026-09-29 18:10 ` Matthew Brost [this message]
2026-09-29 18:10 ` [PATCH 3/3] drm/xe: Do not clear SVM device memory allocations up front Matthew Brost
2026-09-29 18:27 ` sashiko-bot
2026-09-29 18:31 ` Matthew Brost
2026-09-29 20:16 ` Summers, Stuart
2026-09-29 21:14 ` Matthew Brost
2026-09-29 22:05 ` Summers, Stuart
2026-09-29 23:21 ` Matthew Brost
2026-09-29 18:18 ` ✓ CI.KUnit: success for Elide clear on full SVM copies Patchwork
2026-09-29 19:36 ` ✓ Xe.CI.BAT: " Patchwork
2026-09-30 0:17 ` ✗ Xe.CI.FULL: failure " Patchwork
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