Re: [PATCH] drm/xe/xe3p: Read resource copy presence from fuse register

[sashiko-bot@kernel.org]

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [High] xe: VF incorrectly disables BCS0 engine due to missing PF runtime register
--

commit 096730b165de364d3c436c33d0f5b812ac0baee5
Author: Matt Roper <matthew.d.roper@intel.com>

drm/xe/xe3p: Read resource copy presence from fuse register
    
This commit reads the resource copy presence from the fuse register on Xe3p
platforms. The register field is used to determine if the primary resource
copy engine (BCS0) is enabled.

> diff --git a/drivers/gpu/drm/xe/xe_hw_engine.c b/drivers/gpu/drm/xe/xe_hw_engine.c
> index 010499766fce2..519f48d7eca14 100644
> --- a/drivers/gpu/drm/xe/xe_hw_engine.c
> +++ b/drivers/gpu/drm/xe/xe_hw_engine.c
> @@ -801,23 +801,42 @@ static u32 read_svccopy_fuses(struct xe_gt *gt)
>  			     xe_mmio_read32(&gt->mmio, SERVICE_COPY_ENABLE));
>  }
>  
> +static u32 read_rescopy_fuses(struct xe_gt *gt)
> +{
> +	u32 fuse = REG_FIELD_GET(FUSE_RESOURCE_COPY_ENABLE_MASK,
> +				 xe_mmio_read32(&gt->mmio, RESOURCE_COPY_ENABLE));

[Severity: High]
Does this MMIO read fail in SR-IOV VF environments?

Looking at read_rescopy_fuses() in drivers/gpu/drm/xe/xe_hw_engine.c, since
RESOURCE_COPY_ENABLE (0x9174) was not added to the ver_35_runtime_regs array
in drivers/gpu/drm/xe/xe_gt_sriov_pf_service.c, xe_mmio_read32() will fail
to find the register in the PF's shared list.

This causes the VF lookup path via xe_gt_sriov_vf_read32() to return 0,
which would lead to read_copy_fuses() receiving a 0 mask for res_copy_mask
and erroneously disabling the primary resource copy engine (BCS0) for all
Xe3p VFs.

Should RESOURCE_COPY_ENABLE be added to ver_35_runtime_regs to fix this?

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260929-res_copy_fuse-v1-1-80876dba05db@intel.com?part=1