Intel-XE Archive on lore.kernel.org
 help / color / mirror / Atom feed
From: sashiko-bot@kernel.org
To: "Karthik Poosa" <karthik.poosa@intel.com>
Cc: intel-xe@lists.freedesktop.org
Subject: Re: [PATCH v7 01/15] drm/xe/hwmon: Handle pcode read failures of xe_hwmon_pcode_rmw_power_limit
Date: Fri, 02 Oct 2026 09:13:37 +0000	[thread overview]
Message-ID: <20261002091338.430DA1F00893@smtp.kernel.org> (raw)
In-Reply-To: <20261001195033.3466205-2-karthik.poosa@intel.com>

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [Low] drm/xe/hwmon: error code from pcode write is dropped and replaced with -EIO
--

commit a3216689f81fc9f531bd48c8af3db490de1c046b
Author: Karthik Poosa <karthik.poosa@intel.com>
drm/xe/hwmon: Handle pcode read failures of xe_hwmon_pcode_rmw_power_limit

This commit adds error checking to pcode read operations in
xe_hwmon_pcode_rmw_power_limit() and propagates the error up to the callers.
Callers are updated to handle the new return values instead of continuing
with invalid data.

> diff --git a/drivers/gpu/drm/xe/xe_hwmon.c b/drivers/gpu/drm/xe/xe_hwmon.c
> index 5edeac961ec33..92be71f7bc92f 100644
> --- a/drivers/gpu/drm/xe/xe_hwmon.c
> +++ b/drivers/gpu/drm/xe/xe_hwmon.c

[ ... ]

> @@ -679,15 +683,18 @@ xe_hwmon_power_max_interval_store(struct device *dev, struct device_attribute *a
>  
>  	mutex_lock(&hwmon->hwmon_lock);
>  
> -	if (hwmon->xe->info.has_mbx_power_limits)
> -		xe_hwmon_pcode_rmw_power_limit(hwmon, power_attr, channel, PWR_LIM_TIME, rxy);
> -	else
> +	ret = count;
> +	if (hwmon->xe->info.has_mbx_power_limits) {
> +		if (xe_hwmon_pcode_rmw_power_limit(hwmon, power_attr, channel, PWR_LIM_TIME, rxy))
> +			ret = -EIO;

[Severity: Low]
Does this code intentionally discard the specific error code returned by
xe_hwmon_pcode_rmw_power_limit()?

Replacing the actual error (such as -ETIMEDOUT or -ENXIO) with a generic -EIO
might obscure the true cause of the hardware failure and affect userspace
retry logic. Can the returned error code be propagated directly instead?

> +	} else {
>  		r = xe_mmio_rmw32(mmio, xe_hwmon_get_reg(hwmon, REG_PKG_RAPL_LIMIT, channel),
>  				  PWR_LIM_TIME, rxy);
> +	}
>  
>  	mutex_unlock(&hwmon->hwmon_lock);
>  
> -	return count;
> +	return ret;
>  }

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20261001195033.3466205-1-karthik.poosa@intel.com?part=1

  reply	other threads:[~2026-10-02  9:13 UTC|newest]

Thread overview: 21+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-10-01 19:50 [PATCH v7 00/15] drm/xe/hwmon: Update hwmon thermal mailbox Karthik Poosa
2026-10-01 19:50 ` [PATCH v7 01/15] drm/xe/hwmon: Handle pcode read failures of xe_hwmon_pcode_rmw_power_limit Karthik Poosa
2026-10-02  9:13   ` sashiko-bot [this message]
2026-10-05  7:01     ` Poosa, Karthik
2026-10-01 19:50 ` [PATCH v7 02/15] drm/xe/hwmon: Decode mailbox temperature as sign-magnitude Karthik Poosa
2026-10-01 19:50 ` [PATCH v7 03/15] drm/xe/hwmon: Fix memory controller thermal data handling Karthik Poosa
2026-10-01 19:50 ` [PATCH v7 04/15] drm/xe/hwmon: Add helpers to validate thermal sensor readings Karthik Poosa
2026-10-01 19:50 ` [PATCH v7 05/15] drm/xe/hwmon: Handle unavailable memory controller sensors Karthik Poosa
2026-10-01 19:50 ` [PATCH v7 06/15] drm/xe/hwmon: Detect unavailable PCIe thermal sensors Karthik Poosa
2026-10-01 19:50 ` [PATCH v7 07/15] drm/xe/hwmon: Consolidate temperature sensor availability checks Karthik Poosa
2026-10-01 19:50 ` [PATCH v7 08/15] drm/xe/hwmon: Cache temperature availability to reduce probe time Karthik Poosa
2026-10-01 19:50 ` [PATCH v7 09/15] drm/xe/hwmon: use CRI-specific package and VRAM temperature registers Karthik Poosa
2026-10-01 19:50 ` [PATCH v7 10/15] drm/xe/hwmon: Add platform-aware VRAM thermal channel support Karthik Poosa
2026-10-01 19:50 ` [PATCH v7 11/15] drm/xe/hwmon: Decode CRI temperature registers as IEEE-754 Karthik Poosa
2026-10-01 19:50 ` [PATCH v7 12/15] drm/xe/hwmon: Update memory controller temperature offset for CRI Karthik Poosa
2026-10-01 19:50 ` [PATCH v7 13/15] drm/xe/hwmon: Get PCIe temperature sensor offset from xe info Karthik Poosa
2026-10-01 19:50 ` [PATCH v7 14/15] drm/xe/hwmon: Add CRI PCIe temperature sensor offset Karthik Poosa
2026-10-01 19:50 ` [PATCH v7 15/15] drm/xe/hwmon: Simplify temperature channels config Karthik Poosa
2026-10-01 20:00 ` ✓ CI.KUnit: success for drm/xe/hwmon: Update hwmon thermal mailbox (rev4) Patchwork
2026-10-02  0:34 ` ✓ Xe.CI.BAT: " Patchwork
2026-10-02  5:36 ` ✓ Xe.CI.FULL: " Patchwork

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=20261002091338.430DA1F00893@smtp.kernel.org \
    --to=sashiko-bot@kernel.org \
    --cc=intel-xe@lists.freedesktop.org \
    --cc=karthik.poosa@intel.com \
    --cc=sashiko-reviews@lists.linux.dev \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox