From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 44610CA9ED1 for ; Mon, 12 Oct 2026 14:54:59 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 01EA910F1B0; Mon, 12 Oct 2026 14:54:54 +0000 (UTC) Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.16]) by gabe.freedesktop.org (Postfix) with ESMTPS id DEA2610F17F for ; Mon, 12 Oct 2026 14:54:47 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1791816888; x=1823352888; h=from:to:cc:subject:date:message-id:mime-version: content-transfer-encoding; bh=w4ikW2DdILXVoIyNukgbwSiloBkXLFJ/cSaj33FY38E=; b=kAS9aQea+NbIQGXb9coJ/+9KvRfiz94GPKgQA3Obxmb1CDU9BOmIKkTW OldgjkYqhT9315TES9xXy8bkrnVOaiHgZLkipMLgFQB53c3ZifMhOTmgB UtKRA0HKhQ6KzGYgN4DUYhzjrIkvvPYXnfMqefG8qjvLIoIk9o0yn46cN JkTHHk7za5URq6aVuQbw4yy6e7tSV4+cXcJDNQWgK0NGaGFNLi4H8hvQ9 +OXv7IU1uRaNLp0aZY9W9eyc4k4y5iUgL4UMENsf1Iw7G8U3WQrIGxHOB +iw56Na3fELyezIdaODN4rhJBQIoWOqKEmypdrZgFE7Ppdg9HN67RMazX Q==; X-CSE-ConnectionGUID: quAlzh07QyGt8dALPDOYPA== X-CSE-MsgGUID: b7poFuESSyW6IH+pOOZs/A== X-IronPort-AV: E=McAfee;i="6800,10657,11933"; a="513552" X-IronPort-AV: E=Sophos;i="6.27,153,1787036400"; d="scan'208";a="513552" Received: from fmviesa013.fm.intel.com ([10.60.135.153]) by orvoesa108.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 12 Oct 2026 07:54:47 -0700 X-CSE-ConnectionGUID: 3KYqynxISniW5HO9CJYlcg== X-CSE-MsgGUID: r9XqW/WMTiylDLv32Q8Blw== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.27,153,1787036400"; d="scan'208";a="2675253" Received: from gfx-coremm-kmd15.iind.intel.com ([10.223.55.8]) by fmviesa013.fm.intel.com with ESMTP; 12 Oct 2026 07:54:47 -0700 From: Nareshkumar Gollakoti To: intel-xe@lists.freedesktop.org Cc: tejas.upadhyay@intel.com, Nareshkumar Gollakoti Subject: [PATCH v4 0/7] drm/xe: Capture additional HW register state in devcoredump Date: Mon, 12 Oct 2026 20:22:30 +0530 Message-ID: <20261012145237.3788198-1-naresh.kumar.g@intel.com> X-Mailer: git-send-email 2.43.0 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-BeenThere: intel-xe@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel Xe graphics driver List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-xe-bounces@lists.freedesktop.org Sender: "Intel-xe" This series extends the Xe devcoredump with additional hardware register state to improve post-mortem debugging of GPU hangs and faults on Xe3p. Today the devcoredump captures GuC log/CT, engine and submission state. When triaging hangs it is often necessary to also know the static HW configuration (fuses), GuC status/error state, GAM page-fault reporting and L3 node status at the time of the hang. Collecting these at capture time makes the dump self-contained and avoids relying on separate probe-time logging. To do this, the series adds a small generic MMIO register-dump helper (descriptor list -> snapshot -> print/free) and uses it for several register groups. Each group is captured for both the primary GT and, where applicable, the media GT, and is gated to Xe3p (GRAPHICS_VER >= 35). Registers requiring MCR steering are read through xe_gt_mcr_unicast_read_any(); the remaining GAM registers use INSTANCE0 default steering and are read directly. Snapshots are allocated with GFP_ATOMIC as capture runs inside the dma_fence signalling section, matching the surrounding captures, and are freed in the existing devcoredump teardown path. Patches: 1 Add the generic reg-dump helpers and capture GT/media fuse registers. 2 Capture GT and media GuC status/error registers. 3 Print register offsets alongside names in the GuC engine capture output (32- and 64-bit), easing cross-reference with the bspec. 4 Capture the GAM page-fault report head/tail registers. 5 Add the TDL gfx registers to the XeHPG extended GuC capture list. 6 Capture L3 node status registers (MCR, read via unicast_read_any()). 7 Capture additional engine state registers Sample devcoredump output gains the following sections: **** GT Fuse Register Dump **** **** Media GT Fuse Register Dump **** **** GT GuC Register Dump **** **** Media GT GuC Register Dump **** **** GAM PF Report **** **** Node Status **** **** Additional engine state registers **** v3:(Sashiko) - Use the LOW_DW MMIO offset when printing combined 64-bit register values in capture snapshots - Preserve the existing coredump register-name format and append register address as trailing metadata - Replace the render is not awake message with raw POWERGATE_ENABLE bit-state output - Move engine-class-specific registers out of COMMON_BASE_ENGINE_INSTANCE into class-specific capture lists v4: - optimized APIs and reduced few structs(Tejas) - Fixed CI hook error Nareshkumar Gollakoti (7): drm/xe/devcoredump: Capture GT fuse registers in devcoredump drm/xe/devcoredump: Add GuC register snapshot to devcoredump drm/xe/guc: Print register addresses in capture snapshot output drm/xe: dump GAM page fault report registers in devcoredump drm/xe/guc: add TDL,SLICE gfx registers to capture list drm/xe: capture L3 node status registers in devcoredump drm/xe/guc: capture additional engine state registers drivers/gpu/drm/xe/regs/xe_engine_regs.h | 22 ++ drivers/gpu/drm/xe/regs/xe_gt_regs.h | 13 + drivers/gpu/drm/xe/regs/xe_guc_regs.h | 5 + drivers/gpu/drm/xe/xe_devcoredump.c | 320 +++++++++++++++++++++- drivers/gpu/drm/xe/xe_devcoredump_types.h | 66 +++++ drivers/gpu/drm/xe/xe_guc_capture.c | 58 +++- 6 files changed, 472 insertions(+), 12 deletions(-) -- 2.43.0