From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (prime256v1) server-digest SHA256) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id CE8AD606A319 for ; Thu, 22 Oct 2026 13:32:42 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key, unprotected) header.d=intel.com header.i=@intel.com header.a=rsa-sha256 header.s=Intel header.b=YI6WNj/I Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 92488112656; Thu, 22 Oct 2026 13:32:37 +0000 (UTC) Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.17]) by gabe.freedesktop.org (Postfix) with ESMTPS id 35A8B112655 for ; Thu, 22 Oct 2026 13:32:29 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1792675950; x=1824211950; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=jRzNU2aXPV7G885NUXQBqBCLTBnlOcmWdEASpV26xoc=; b=YI6WNj/I1z8SCIPPzOu1Iz7LYAZtWZJCqOSdTnJZSwf7Ctb+V6dVB8Ti EtvmXx2LVAxZOMyIIkrePjGy8waBdWBdw7JFynWg1FJb02VIaJfuMyUYD P7Re8aYtBJX7qE9JaX1SokcwrYBbtffw0aVcnpwfXXMqNmgamSgzMBSjf Z17whVeBAVug8WptQgtbaVNUxOk+vBwwPo290Lam6QdCt4kFp1axH4I7Z +Ezkm8fgCBUxS6r9u/Qnw4T9hiiBrZaR/SpXupzQuSYuvktBRG0xf0Fk1 PK2oL9KvGkypB+IMIM9usWG/YgRqX10g2l5pVVrqcWXBlPkYL0L5sQsUv g==; X-CSE-ConnectionGUID: uG46FXDYRPyW6qC0ODxdCw== X-CSE-MsgGUID: u7XehORnSeGfkHViYlZ0zw== X-IronPort-AV: E=McAfee;i="6800,10657,11942"; a="1439226" X-IronPort-AV: E=Sophos;i="6.27,172,1787036400"; d="scan'208";a="1439226" Received: from fmviesa001.fm.intel.com ([10.60.135.141]) by orvoesa109.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 22 Oct 2026 06:32:29 -0700 X-CSE-ConnectionGUID: KENLKzUHT+OhXyfPFlWxDw== X-CSE-MsgGUID: Q4JEjSurSdShNtyjujkq+g== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.27,172,1787036400"; d="scan'208";a="3700772" Received: from gfx-coremm-kmd15.iind.intel.com ([10.223.55.8]) by fmviesa001.fm.intel.com with ESMTP; 22 Oct 2026 06:32:27 -0700 From: Nareshkumar Gollakoti To: intel-xe@lists.freedesktop.org Cc: tejas.upadhyay@intel.com, Nareshkumar Gollakoti Subject: [PATCH v5 3/7] drm/xe/guc: Print register addresses in capture snapshot output Date: Thu, 22 Oct 2026 18:59:53 +0530 Message-ID: <20261022132957.2479469-4-naresh.kumar.g@intel.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20261022132957.2479469-1-naresh.kumar.g@intel.com> References: <20261022132957.2479469-1-naresh.kumar.g@intel.com> X-Archived-By: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-BeenThere: intel-xe@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel Xe graphics driver List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "Intel-xe" X-Spam-Status: No, score=-18.8 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER,INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE, SPF_PASS,USER_AGENT_GIT autolearn=ham autolearn_force=no version=4.0.1 X-Spam-Checker-Version: SpamAssassin 4.0.1 (2024-03-26) on aws-us-west-2-korg-listserv-alma10-1 Include register offsets in GuC capture snapshot print output for both 32-bit and 64-bit registers. When dumping captured engine register state, print each register name alongside its MMIO offset to make the snapshot output easier to cross-reference with register definitions and hardware debug documentation. This improves postmortem analysis without changing capture contents. v2:(Sashiko) - Ensure lower DWORD prints v3:(Sashiko) - Use the LOW_DW MMIO offset(capture in last_address) when combined 64bit register values in the dump instead of HI_SW offset - preserve existing coredump register-name format and append register address as trailing metadata as a debug info and avoids disrupting existing format Signed-off-by: Nareshkumar Gollakoti --- drivers/gpu/drm/xe/xe_guc_capture.c | 18 ++++++++++++++---- 1 file changed, 14 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/xe/xe_guc_capture.c b/drivers/gpu/drm/xe/xe_guc_capture.c index 5a4d085660a2..3e99aef53b46 100644 --- a/drivers/gpu/drm/xe/xe_guc_capture.c +++ b/drivers/gpu/drm/xe/xe_guc_capture.c @@ -1716,6 +1716,7 @@ snapshot_print_by_list_order(struct xe_hw_engine_snapshot *snapshot, struct drm_ struct xe_devcoredump_snapshot *devcore_snapshot = &devcoredump->snapshot; struct gcap_reg_list_info *reginfo = NULL; u32 i, last_value = 0; + u32 last_address = 0; bool low32_ready = false; if (!list || !list->list || list->num_regs == 0) @@ -1743,6 +1744,7 @@ snapshot_print_by_list_order(struct xe_hw_engine_snapshot *snapshot, struct drm_ switch (reg_desc->data_type) { case REG_64BIT_LOW_DW: last_value = value; + last_address = reg_desc->reg.addr; /* * A 64 bit register define requires 2 consecutive @@ -1774,7 +1776,11 @@ snapshot_print_by_list_order(struct xe_hw_engine_snapshot *snapshot, struct drm_ XE_WARN_ON(!low32_ready); low32_ready = false; - drm_printf(p, "\t%s: 0x%016llx\n", reg_desc->regname, value_qw); + drm_printf(p, "\t%s: 0x%016llx [addr=0x%x]\n", + reg_desc->regname, + value_qw, + last_address); + break; } @@ -1788,10 +1794,14 @@ snapshot_print_by_list_order(struct xe_hw_engine_snapshot *snapshot, struct drm_ XE_WARN_ON(low32_ready); if (FIELD_GET(GUC_REGSET_STEERING_NEEDED, reg_desc->flags)) - drm_printf(p, "\t%s[%u]: 0x%08x\n", reg_desc->regname, - reg_desc->dss_id, value); + drm_printf(p, "\t%s[%u]: 0x%08x [addr=0x%x]\n", + reg_desc->regname, + reg_desc->dss_id, value, reg_desc->reg.addr); + else - drm_printf(p, "\t%s: 0x%08x\n", reg_desc->regname, value); + drm_printf(p, "\t%s: 0x%08x [addr=0x%x]\n", + reg_desc->regname, value, reg_desc->reg.addr); + break; } -- 2.43.0