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From: Maarten Lankhorst <dev@lankhorst.se>
To: intel-xe@lists.freedesktop.org
Cc: Maarten Lankhorst <dev@lankhorst.se>
Subject: [PATCH v2 2/2] drm/xe/display: Use xe_bo_addr_iter in remapped DPT pinning
Date: Fri, 23 Oct 2026 13:46:16 +0200	[thread overview]
Message-ID: <20261023114616.735366-2-dev@lankhorst.se> (raw)
In-Reply-To: <20261023114616.735366-1-dev@lankhorst.se>

Right now we're using xe_bo_addr() on each individual address, which gives
problems at larger resolution and sizes, since it's a O(N²).

By using xe_bo_addr_iter_first() + xe_bo_addr_iter_addr(), the time
complexity is reduced again to O(N).

To fix rotated pinning requires some thinking.

Signed-off-by: Maarten Lankhorst <dev@lankhorst.se>
---
Changes since v1:
- handle plane->src_stride != plane->width
---
 drivers/gpu/drm/xe/display/xe_fb_pin.c | 27 ++++++++++++++------------
 1 file changed, 15 insertions(+), 12 deletions(-)

diff --git a/drivers/gpu/drm/xe/display/xe_fb_pin.c b/drivers/gpu/drm/xe/display/xe_fb_pin.c
index e09116265ae95..95f0cbc8b2bb2 100644
--- a/drivers/gpu/drm/xe/display/xe_fb_pin.c
+++ b/drivers/gpu/drm/xe/display/xe_fb_pin.c
@@ -17,6 +17,7 @@
 #include "xe_ggtt.h"
 #include "xe_pat.h"
 #include "xe_pm.h"
+#include "xe_res_cursor.h"
 #include "xe_vram_types.h"
 
 static void
@@ -68,14 +69,14 @@ write_dpt_remapped_linear(struct xe_bo *bo, struct iosys_map *map,
 	const u64 pte = xe_ggtt_encode_pte_flags(ggtt, bo,
 						 xe_cache_pat_idx(xe, XE_CACHE_NONE));
 	unsigned int offset = plane->offset * XE_PAGE_SIZE;
-	unsigned int size = plane->size;
+	unsigned int size = plane->size * XE_PAGE_SIZE;
+	struct xe_res_cursor cur;
 
-	while (size--) {
-		u64 addr = xe_bo_addr(bo, offset, XE_PAGE_SIZE);
+	for (xe_bo_addr_iter_first(bo, &cur, offset, size); cur.remaining; xe_res_next(&cur, XE_PAGE_SIZE)) {
+		u64 addr = xe_bo_addr_iter_addr(&cur);
 
 		iosys_map_wr(map, dest, u64, addr | pte);
 		dest += sizeof(u64);
-		offset += XE_PAGE_SIZE;
 	}
 
 	return dest;
@@ -90,20 +91,22 @@ write_dpt_remapped_tiled(struct xe_bo *bo, struct iosys_map *map,
 	struct xe_ggtt *ggtt = xe_device_get_root_tile(xe)->mem.ggtt;
 	const u64 pte = xe_ggtt_encode_pte_flags(ggtt, bo,
 						 xe_cache_pat_idx(xe, XE_CACHE_NONE));
-	unsigned int offset, column, row;
+	u32 offset = plane->offset * XE_PAGE_SIZE;
+	struct xe_res_cursor cur;
 
-	for (row = 0; row < plane->height; row++) {
-		offset = (plane->offset + plane->src_stride * row) *
-			 XE_PAGE_SIZE;
-
-		for (column = 0; column < plane->width; column++) {
-			u64 addr = xe_bo_addr(bo, offset, XE_PAGE_SIZE);
+	xe_bo_addr_iter_first(bo, &cur, offset, plane->height * plane->src_stride * XE_PAGE_SIZE);
+	while (cur.remaining) {
+		for (u32 column = 0; column < plane->width; column++) {
+			u64 addr = xe_bo_addr_iter_addr(&cur);
 
 			iosys_map_wr(map, dest, u64, addr | pte);
 			dest += sizeof(u64);
-			offset += XE_PAGE_SIZE;
+			xe_res_next(&cur, XE_PAGE_SIZE);
 		}
 
+		if (plane->src_stride != plane->width)
+			xe_res_next(&cur, (plane->src_stride - plane->width) * XE_PAGE_SIZE);
+
 		dest = write_dpt_padding(map, dest,
 					 plane->dst_stride - plane->width);
 	}
-- 
2.55.0


  reply	other threads:[~2026-10-23 11:46 UTC|newest]

Thread overview: 11+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-10-23 11:46 [PATCH v2 1/2] drm/xe/bo: Add xe_bo_addr_iter Maarten Lankhorst
2026-10-23 11:46 ` Maarten Lankhorst [this message]
2026-10-23 11:59   ` [PATCH v2 2/2] drm/xe/display: Use xe_bo_addr_iter in remapped DPT pinning sashiko-bot
2026-10-23 12:30     ` Maarten Lankhorst
2026-10-23 12:08 ` ✗ CI.checkpatch: warning for series starting with [v2,1/2] drm/xe/bo: Add xe_bo_addr_iter Patchwork
2026-10-23 12:10 ` ✓ CI.KUnit: success " Patchwork
2026-10-23 12:47 ` ✓ Xe.CI.BAT: " Patchwork
2026-10-23 17:55 ` ✗ Xe.CI.FULL: failure " Patchwork
2026-10-27  4:13 ` Murthy, Arun R
2026-10-27  9:45   ` Maarten Lankhorst
2026-10-27 14:49     ` Murthy, Arun R

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