public inbox for intel-xe@lists.freedesktop.org
 help / color / mirror / Atom feed
From: Matthew Auld <matthew.auld@intel.com>
To: Jia Yao <jia.yao@intel.com>, intel-xe@lists.freedesktop.org
Cc: stable@vger.kernel.org, Shuicheng Lin <shuicheng.lin@intel.com>,
	Mathew Alwin <alwin.mathew@intel.com>,
	Michal Mrozek <michal.mrozek@intel.com>,
	Matthew Brost <matthew.brost@intel.com>
Subject: Re: [PATCH v5 2/2] drm/xe: Reject coh_none PAT index for CPU_ADDR_MIRROR
Date: Mon, 16 Mar 2026 11:40:24 +0000	[thread overview]
Message-ID: <20732332-b75f-43e0-a244-210b47b44dc5@intel.com> (raw)
In-Reply-To: <20260316072257.255372-3-jia.yao@intel.com>

On 16/03/2026 07:22, Jia Yao wrote:
> Add validation in xe_vm_bind_ioctl() to reject PAT indices with
> XE_COH_NONE coherency mode when used with
> DRM_XE_VM_BIND_FLAG_CPU_ADDR_MIRROR, consistent with the existing
> validation for DRM_XE_VM_BIND_OP_MAP_USERPTR.
> 
> CPU address mirror mappings use system memory which is CPU cached,
> making them incompatible with COH_NONE PAT index. Using COH_NONE with
> CPU cached buffers is a security issue: GPU can bypass CPU caches and
> directly read stale sensitive data from DRAM, potentially leaking data
> from previously freed pages.
> 
> Although CPU_ADDR_MIRROR mappings don't create actual memory mappings
> (the range is reserved for dynamic mapping on GPU page faults), the
> underlying system memory is still CPU cached, so the same PAT coherency
> restrictions as MAP_USERPTR should apply.
> 
> Fixes: ada7486c5668 ("drm/xe: Implement madvise ioctl for xe")

Is this the right fixes tag?

> Cc: stable@vger.kernel.org # v6.18
> Cc: Shuicheng Lin <shuicheng.lin@intel.com>
> Cc: Mathew Alwin <alwin.mathew@intel.com>
> Cc: Michal Mrozek <michal.mrozek@intel.com>
> Cc: Matthew Brost <matthew.brost@intel.com>
> Cc: Matthew Auld <matthew.auld@intel.com>
> Signed-off-by: Jia Yao <jia.yao@intel.com>

As discussed offline, I think this is needed. My understanding is that 
when binding an svm range we use the parent vma pat index, and without 
using the madvise pat control, the default pat index is whatever the 
user selects here, which could be incoherent, and on least igpu that 
will be problematic when accessing CPU cached system memory.

Reviewed-by: Matthew Auld <matthew.auld@intel.com>

> ---
>   drivers/gpu/drm/xe/xe_vm.c | 2 +-
>   1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/xe/xe_vm.c b/drivers/gpu/drm/xe/xe_vm.c
> index 5572e12c2a7e..1c4b4a5eeadb 100644
> --- a/drivers/gpu/drm/xe/xe_vm.c
> +++ b/drivers/gpu/drm/xe/xe_vm.c
> @@ -3491,7 +3491,7 @@ static int vm_bind_ioctl_check_args(struct xe_device *xe, struct xe_vm *vm,
>   		    XE_IOCTL_DBG(xe, obj &&
>   				 op == DRM_XE_VM_BIND_OP_MAP_USERPTR) ||
>   		    XE_IOCTL_DBG(xe, coh_mode == XE_COH_NONE &&
> -				 op == DRM_XE_VM_BIND_OP_MAP_USERPTR) ||
> +				 (op == DRM_XE_VM_BIND_OP_MAP_USERPTR || is_cpu_addr_mirror)) ||
>   		    XE_IOCTL_DBG(xe, comp_en &&
>   				 op == DRM_XE_VM_BIND_OP_MAP_USERPTR) ||
>   		    XE_IOCTL_DBG(xe, op == DRM_XE_VM_BIND_OP_MAP_USERPTR &&


  reply	other threads:[~2026-03-16 11:40 UTC|newest]

Thread overview: 48+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-01-29  0:01 [PATCH] drm/xe: Reject coh_none PAT index for CPU cached memory in madvise Jia Yao
2026-01-29  0:09 ` ✓ CI.KUnit: success for " Patchwork
2026-01-29  0:49 ` ✓ Xe.CI.BAT: " Patchwork
2026-01-29  4:35 ` [PATCH] " Matthew Brost
2026-01-29  5:51 ` [PATCH v2] " Jia Yao
2026-01-29  9:58   ` Matthew Auld
2026-01-29  6:44 ` ✓ CI.KUnit: success for drm/xe: Reject coh_none PAT index for CPU cached memory in madvise (rev2) Patchwork
2026-01-29  7:24 ` ✓ Xe.CI.BAT: " Patchwork
2026-01-30 22:07 ` [PATCH v3] drm/xe/uapi: Reject coh_none PAT index for CPU cached memory in madvise Jia Yao
2026-02-03  2:54   ` Lin, Shuicheng
2026-02-04 15:13   ` Souza, Jose
2026-01-30 23:05 ` ✓ CI.KUnit: success for drm/xe: Reject coh_none PAT index for CPU cached memory in madvise (rev3) Patchwork
2026-01-30 23:44 ` ✓ Xe.CI.BAT: " Patchwork
2026-02-03 15:48 ` [PATCH v4] drm/xe/uapi: Reject coh_none PAT index for CPU cached memory in madvise Jia Yao
2026-02-03 16:38   ` Matthew Auld
2026-02-03 16:59     ` Yao, Jia
2026-03-10 14:50   ` Mrozek, Michal
2026-02-03 16:14 ` ✓ CI.KUnit: success for drm/xe: Reject coh_none PAT index for CPU cached memory in madvise (rev4) Patchwork
2026-02-03 17:07 ` ✗ Xe.CI.BAT: failure " Patchwork
2026-02-04  8:47 ` ✗ Xe.CI.FULL: " Patchwork
2026-02-04 21:13 ` ✓ CI.KUnit: success for drm/xe: Reject coh_none PAT index for CPU cached memory in madvise (rev5) Patchwork
2026-02-04 21:47 ` ✓ Xe.CI.BAT: " Patchwork
2026-02-05 10:35 ` ✗ Xe.CI.FULL: failure " Patchwork
2026-03-16  7:22 ` [PATCH v5 0/2] drm/xe: PAT index validation for CPU_ADDR_MIRROR and Jia Yao
2026-03-16  7:22   ` [PATCH v5 1/2] drm/xe/uapi: Reject coh_none PAT index for CPU cached memory in madvise Jia Yao
2026-03-16 10:59     ` Matthew Auld
2026-03-16 15:29       ` Lin, Shuicheng
2026-03-16  7:22   ` [PATCH v5 2/2] drm/xe: Reject coh_none PAT index for CPU_ADDR_MIRROR Jia Yao
2026-03-16 11:40     ` Matthew Auld [this message]
2026-03-16  7:29 ` ✓ CI.KUnit: success for drm/xe: Reject coh_none PAT index for CPU cached memory in madvise (rev6) Patchwork
2026-03-16  8:18 ` ✓ Xe.CI.BAT: " Patchwork
2026-03-16 16:42 ` [PATCH v5 0/2] drm/xe: PAT index validation for CPU_ADDR_MIRROR and madvise Jia Yao
2026-03-16 16:42   ` [PATCH v6 1/2] drm/xe/uapi: Reject coh_none PAT index for CPU cached memory in madvise Jia Yao
2026-03-16 16:42   ` [PATCH v6 2/2] drm/xe: Reject coh_none PAT index for CPU_ADDR_MIRROR Jia Yao
2026-03-17 10:45     ` Matthew Auld
2026-03-16 21:28 ` ✓ CI.KUnit: success for drm/xe: Reject coh_none PAT index for CPU cached memory in madvise (rev7) Patchwork
2026-03-16 22:03 ` ✓ Xe.CI.BAT: " Patchwork
2026-03-17 21:17 ` ✗ Xe.CI.FULL: failure " Patchwork
2026-03-19 11:58 ` [PATCH v7 0/2] drm/xe: PAT index validation for CPU_ADDR_MIRROR and madvise Jia Yao
2026-03-19 11:58   ` [PATCH v7 1/2] drm/xe/uapi: Reject coh_none PAT index for CPU cached memory in madvise Jia Yao
2026-03-19 11:58   ` [PATCH v7 2/2] drm/xe: Reject coh_none PAT index for CPU_ADDR_MIRROR Jia Yao
2026-03-19 12:24 ` ✓ CI.KUnit: success for drm/xe: Reject coh_none PAT index for CPU cached memory in madvise (rev8) Patchwork
2026-03-19 13:12 ` ✓ Xe.CI.BAT: " Patchwork
2026-03-20 14:04 ` ✗ Xe.CI.FULL: failure " Patchwork
2026-04-15  6:19 ` [PATCH v8 0/2] drm/xe: Reject unsafe PAT indices for CPU cached memory Jia Yao
2026-04-15  6:19   ` [PATCH v8 1/2] drm/xe/uapi: Reject coh_none PAT index for CPU cached memory in madvise Jia Yao
2026-04-15  6:19   ` [PATCH v8 2/2] drm/xe: Reject coh_none PAT index for CPU_ADDR_MIRROR Jia Yao
2026-04-15 12:15     ` Matthew Auld

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=20732332-b75f-43e0-a244-210b47b44dc5@intel.com \
    --to=matthew.auld@intel.com \
    --cc=alwin.mathew@intel.com \
    --cc=intel-xe@lists.freedesktop.org \
    --cc=jia.yao@intel.com \
    --cc=matthew.brost@intel.com \
    --cc=michal.mrozek@intel.com \
    --cc=shuicheng.lin@intel.com \
    --cc=stable@vger.kernel.org \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox