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mx.microsoft.com 1; spf=pass smtp.mailfrom=intel.com; dmarc=pass action=none header.from=intel.com; dkim=pass header.d=intel.com; arc=none Authentication-Results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=intel.com; Received: from IA0PR11MB7307.namprd11.prod.outlook.com (2603:10b6:208:437::10) by CY5PR11MB6187.namprd11.prod.outlook.com (2603:10b6:930:25::11) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.9253.13; Thu, 23 Oct 2025 07:49:13 +0000 Received: from IA0PR11MB7307.namprd11.prod.outlook.com ([fe80::dafa:d38d:8ac1:e843]) by IA0PR11MB7307.namprd11.prod.outlook.com ([fe80::dafa:d38d:8ac1:e843%6]) with mapi id 15.20.9253.011; Thu, 23 Oct 2025 07:49:11 +0000 Message-ID: <212d5122-31ab-4341-b406-877baf36dbef@intel.com> Date: Thu, 23 Oct 2025 13:19:04 +0530 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 10/25] drm/i915/ltphy: Enable SSC during port clock programming To: Suraj Kandpal , , CC: , , , References: <20251015040817.3431297-1-suraj.kandpal@intel.com> <20251015040817.3431297-11-suraj.kandpal@intel.com> Content-Language: en-US From: "Murthy, Arun R" In-Reply-To: <20251015040817.3431297-11-suraj.kandpal@intel.com> Content-Type: text/plain; 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We logically > determine if ssc is enabled or not while we calculate our state. > > Bspec: 74492, 74667 > Signed-off-by: Suraj Kandpal > --- Reviewed-by: Arun R Murthy Thanks and Regards, Arun R Murthy ------------------- > drivers/gpu/drm/i915/display/intel_lt_phy.c | 26 +++++++++++++++++++++ > 1 file changed, 26 insertions(+) > > diff --git a/drivers/gpu/drm/i915/display/intel_lt_phy.c b/drivers/gpu/drm/i915/display/intel_lt_phy.c > index 8cd0009609d4..6ee785fbcad2 100644 > --- a/drivers/gpu/drm/i915/display/intel_lt_phy.c > +++ b/drivers/gpu/drm/i915/display/intel_lt_phy.c > @@ -15,6 +15,7 @@ > #include "intel_dpll_mgr.h" > #include "intel_lt_phy.h" > #include "intel_lt_phy_regs.h" > +#include "intel_panel.h" > #include "intel_psr.h" > #include "intel_tc.h" > > @@ -1109,6 +1110,12 @@ intel_lt_phy_program_port_clock_ctl(struct intel_encoder *encoder, > else > val |= XELPDP_DDI_CLOCK_SELECT_PREP(display, XELPDP_DDI_CLOCK_SELECT_MAXPCLK); > > + /* DP2.0 10G and 20G rates enable MPLLA*/ > + if (crtc_state->port_clock == 1000000 || crtc_state->port_clock == 2000000) > + val |= XELPDP_SSC_ENABLE_PLLA; > + else > + val |= crtc_state->dpll_hw_state.ltpll.ssc_enabled ? XELPDP_SSC_ENABLE_PLLB : 0; > + > intel_de_rmw(display, XELPDP_PORT_CLOCK_CTL(display, encoder->port), > XELPDP_LANE1_PHY_CLOCK_SELECT | XELPDP_FORWARD_CLOCK_UNGATE | > XELPDP_DDI_CLOCK_SELECT_MASK(display) | XELPDP_SSC_ENABLE_PLLA | > @@ -1212,6 +1219,23 @@ intel_lt_phy_pll_tables_get(struct intel_crtc_state *crtc_state, > return NULL; > } > > +static bool > +intel_lt_phy_pll_is_ssc_enabled(struct intel_crtc_state *crtc_state, > + struct intel_encoder *encoder) > +{ > + struct intel_display *display = to_intel_display(encoder); > + > + if (intel_crtc_has_dp_encoder(crtc_state)) { > + if (intel_panel_use_ssc(display)) { > + struct intel_dp *intel_dp = enc_to_intel_dp(encoder); > + > + return (intel_dp->dpcd[DP_MAX_DOWNSPREAD] & DP_MAX_DOWNSPREAD_0_5); > + } > + } > + > + return false; > +} > + > int > intel_lt_phy_pll_calc_state(struct intel_crtc_state *crtc_state, > struct intel_encoder *encoder) > @@ -1230,6 +1254,8 @@ intel_lt_phy_pll_calc_state(struct intel_crtc_state *crtc_state, > if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP)) > crtc_state->dpll_hw_state.ltpll.config[2] = 1; > } > + crtc_state->dpll_hw_state.ltpll.ssc_enabled = > + intel_lt_phy_pll_is_ssc_enabled(crtc_state, encoder); > return 0; > } > }