[PATCH 06/10] drm/i915/color: Extract HDR pre-CSC LUT programming to helper function

Chaitanya Kumar Borah
2026-03-06T17:19:04Z

From: Pranay Samala <pranay.samala@intel.com>

As we prepare to add support for LUT programming in SDR planes,
refactor HDR plane pre-CSC LUT programming to a helper.

Signed-off-by: Pranay Samala <pranay.samala@intel.com>
Signed-off-by: Chaitanya Kumar Borah <chaitanya.kumar.borah@intel.com>
---
drivers/gpu/drm/i915/display/intel_color.c | 92 ++++++++++++----------
1 file changed, 51 insertions(+), 41 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_color.c b/drivers/gpu/drm/i915/display/intel_color.c
index 6d1cffc6d2be..17ab4364faea 100644
--- a/drivers/gpu/drm/i915/display/intel_color.c
+++ b/drivers/gpu/drm/i915/display/intel_color.c
@@ -3943,6 +3943,55 @@ xelpd_load_plane_csc_matrix(struct intel_dsb *dsb,
ctm_to_twos_complement(input[11], 0, 12));
}

+static void
+xelpd_load_hdr_pre_csc_lut(struct intel_display *display,
+ struct intel_dsb *dsb,
+ enum pipe pipe,
+ enum plane_id plane,
+ const struct drm_color_lut32 *pre_csc_lut)
+{
+ u32 lut_size = 128;
+ u32 lut_val;
+ int i;
+
+ intel_de_write_dsb(display, dsb,
+ PLANE_PRE_CSC_GAMC_INDEX_ENH(pipe, plane, 0),
+ PLANE_PAL_PREC_AUTO_INCREMENT);
+
+ if (pre_csc_lut) {
+ for (i = 0; i < lut_size; i++) {
+ lut_val = drm_color_lut32_extract(pre_csc_lut[i].green, 24);
+
+ intel_de_write_dsb(display, dsb,
+ PLANE_PRE_CSC_GAMC_DATA_ENH(pipe, plane, 0),
+ lut_val);
+ }
+
+ /* Program the max register to clamp values > 1.0. */
+ /* TODO: Restrict to 0x7ffffff */
+ do {
+ intel_de_write_dsb(display, dsb,
+ PLANE_PRE_CSC_GAMC_DATA_ENH(pipe, plane, 0),
+ (1 << 24));
+ } while (i++ < 130);
+ } else {
+ for (i = 0; i < lut_size; i++) {
+ lut_val = (i * ((1 << 24) - 1)) / (lut_size - 1);
+
+ intel_de_write_dsb(display, dsb,
+ PLANE_PRE_CSC_GAMC_DATA_ENH(pipe, plane, 0), lut_val);
+ }
+
+ do {
+ intel_de_write_dsb(display, dsb,
+ PLANE_PRE_CSC_GAMC_DATA_ENH(pipe, plane, 0),
+ 1 << 24);
+ } while (i++ < 130);
+ }
+
+ intel_de_write_dsb(display, dsb, PLANE_PRE_CSC_GAMC_INDEX_ENH(pipe, plane, 0), 0);
+}
+
static void
xelpd_program_plane_pre_csc_lut(struct intel_dsb *dsb,
const struct intel_plane_state *plane_state)
@@ -3952,48 +4001,9 @@ xelpd_program_plane_pre_csc_lut(struct intel_dsb *dsb,
enum pipe pipe = to_intel_plane(state->plane)->pipe;
enum plane_id plane = to_intel_plane(state->plane)->id;
const struct drm_color_lut32 *pre_csc_lut = plane_state->hw.degamma_lut->data;
- u32 i, lut_size;

- if (icl_is_hdr_plane(display, plane)) {
- lut_size = 128;
-
- intel_de_write_dsb(display, dsb,
- PLANE_PRE_CSC_GAMC_INDEX_ENH(pipe, plane, 0),
- PLANE_PAL_PREC_AUTO_INCREMENT);
-
- if (pre_csc_lut) {
- for (i = 0; i < lut_size; i++) {
- u32 lut_val = drm_color_lut32_extract(pre_csc_lut[i].green, 24);
-
- intel_de_write_dsb(display, dsb,
- PLANE_PRE_CSC_GAMC_DATA_ENH(pipe, plane, 0),
- lut_val);
- }
-
- /* Program the max register to clamp values > 1.0. */
- /* TODO: Restrict to 0x7ffffff */
- do {
- intel_de_write_dsb(display, dsb,
- PLANE_PRE_CSC_GAMC_DATA_ENH(pipe, plane, 0),
- (1 << 24));
- } while (i++ < 130);
- } else {
- for (i = 0; i < lut_size; i++) {
- u32 v = (i * ((1 << 24) - 1)) / (lut_size - 1);
-
- intel_de_write_dsb(display, dsb,
- PLANE_PRE_CSC_GAMC_DATA_ENH(pipe, plane, 0), v);
- }
-
- do {
- intel_de_write_dsb(display, dsb,
- PLANE_PRE_CSC_GAMC_DATA_ENH(pipe, plane, 0),
- 1 << 24);
- } while (i++ < 130);
- }
-
- intel_de_write_dsb(display, dsb, PLANE_PRE_CSC_GAMC_INDEX_ENH(pipe, plane, 0), 0);
- }
+ if (icl_is_hdr_plane(display, plane))
+ xelpd_load_hdr_pre_csc_lut(display, dsb, pipe, plane, pre_csc_lut);
}

static void
--
2.25.1