[PATCH v2 09/13] drm/i915/display: PSR2: Set idle_frames to 0 for DC3CO

Dibin Moolakadan Subrahmanian
2026-04-22T16:26:28Z

Force idle_frames to 0 when DC3CO is eligible.

Changes in v2:
- Extend existing Wa_16025596647 condition
instead of adding a new if block (Uma Shankar)

BSpec: 75253
Signed-off-by: Dibin Moolakadan Subrahmanian <dibin.moolakadan.subrahmanian@intel.com>
---
drivers/gpu/drm/i915/display/intel_psr.c | 9 +++++----
1 file changed, 5 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
index 2e0478e3d560..ff9ce7d2a5aa 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.c
+++ b/drivers/gpu/drm/i915/display/intel_psr.c
@@ -1069,10 +1069,11 @@ static void hsw_activate_psr2(struct intel_dp *intel_dp)
u32 psr_val = 0;
u8 idle_frames;

- /* Wa_16025596647 */
- if ((DISPLAY_VER(display) == 20 ||
- IS_DISPLAY_VERx100_STEP(display, 3000, STEP_A0, STEP_B0)) &&
- is_dc5_dc6_blocked(intel_dp) && intel_dp->psr.pkg_c_latency_used)
+ /* DC3CO / Wa_16025596647 */
+ if (intel_dp->psr.dc3co_eligible ||
+ ((DISPLAY_VER(display) == 20 ||
+ IS_DISPLAY_VERx100_STEP(display, 3000, STEP_A0, STEP_B0)) &&
+ is_dc5_dc6_blocked(intel_dp) && intel_dp->psr.pkg_c_latency_used))
idle_frames = 0;
else
idle_frames = psr_compute_idle_frames(intel_dp);
--
2.43.0