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mx.microsoft.com 1; spf=pass smtp.mailfrom=intel.com; dmarc=pass action=none header.from=intel.com; dkim=pass header.d=intel.com; arc=none Authentication-Results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=intel.com; Received: from DM4PR11MB7183.namprd11.prod.outlook.com (2603:10b6:8:111::10) by DS4PPF07B018B9F.namprd11.prod.outlook.com (2603:10b6:f:fc02::7) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.21.181.8; Wed, 1 Jul 2026 06:32:25 +0000 Received: from DM4PR11MB7183.namprd11.prod.outlook.com ([fe80::d9c7:d2fb:680d:1ee1]) by DM4PR11MB7183.namprd11.prod.outlook.com ([fe80::d9c7:d2fb:680d:1ee1%5]) with mapi id 15.21.0159.018; Wed, 1 Jul 2026 06:32:23 +0000 Message-ID: <2bf3f7a5-deff-472d-ac70-801cea21145b@intel.com> Date: Wed, 1 Jul 2026 12:02:16 +0530 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 1/1] drm/i915/display/psr: Block DC3CO entry during active frame To: "Kandpal, Suraj" , "intel-gfx@lists.freedesktop.org" , "intel-xe@lists.freedesktop.org" CC: "Manna, Animesh" , "Shankar, Uma" References: <20260630085928.1317279-1-dibin.moolakadan.subrahmanian@intel.com> <20260630085928.1317279-2-dibin.moolakadan.subrahmanian@intel.com> Content-Language: en-US From: Dibin Moolakadan Subrahmanian In-Reply-To: Content-Type: text/plain; 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I'll remove it in the next version. >> On Xe3P onwards, when PSR2 is enabled on a panel that does not support Early >> Transport, DC3CO can be entered in the middle of an active frame. This >> prevents the pipe from completing the frame and leaves it in a bad state that >> does not recover well, causing visible corruption on screen. >> >> Set CHICKEN_DCPR_4 bit 24 in the PSR2 enable path when Early Transport is >> not in use, to notify DMC to prevent DC3CO entry. >> >> BSpec: 71483 > Add 75253 here too Will add this in the next version. >> Signed-off-by: Dibin Moolakadan Subrahmanian >> >> --- >> .../gpu/drm/i915/display/intel_display_regs.h | 3 +++ >> drivers/gpu/drm/i915/display/intel_psr.c | 16 ++++++++++++++++ >> 2 files changed, 19 insertions(+) >> >> diff --git a/drivers/gpu/drm/i915/display/intel_display_regs.h >> b/drivers/gpu/drm/i915/display/intel_display_regs.h >> index 39e50423132f..754bb9b188b6 100644 >> --- a/drivers/gpu/drm/i915/display/intel_display_regs.h >> +++ b/drivers/gpu/drm/i915/display/intel_display_regs.h >> @@ -1747,6 +1747,9 @@ >> #define XELPD_CHICKEN_DCPR_3 _MMIO(0x46438) >> #define DMD_RSP_TIMEOUT_DISABLE REG_BIT(19) >> >> +#define XE3LPD_CHICKEN_DCPR_4 _MMIO(0x454a0) > This should be XE3P_CHICKEN_DCPR_4 Will correct this in the next version. > >> +#define DCPR4_BLOCK_DC3CO_ACTIVE_FRAME REG_BIT(24) >> + >> #define SKL_DFSM _MMIO(0x51000) >> #define SKL_DFSM_DISPLAY_PM_DISABLE (1 << 27) >> #define SKL_DFSM_DISPLAY_HDCP_DISABLE (1 << 25) >> diff --git a/drivers/gpu/drm/i915/display/intel_psr.c >> b/drivers/gpu/drm/i915/display/intel_psr.c >> index 911afb9cb24e..ad6ece3ce04d 100644 >> --- a/drivers/gpu/drm/i915/display/intel_psr.c >> +++ b/drivers/gpu/drm/i915/display/intel_psr.c >> @@ -2103,6 +2103,18 @@ static void intel_psr_enable_source(struct intel_dp >> *intel_dp, >> else if (display->platform.alderlake_p) >> intel_de_rmw(display, CLKGATE_DIS_MISC, 0, >> CLKGATE_DIS_MISC_DMASC_GATING_DIS); >> + >> + /* >> + * HSD: 14026643300 > This can be WA: > >> + * On Xe3P+, restrict DC3CO entry during active frame when >> PSR2 is >> + * enabled without panel Early Transport; required to avoid >> pipe bad state. >> + * DMC honours CHICKEN_DCPR_4 bit 24 to block DC3CO entry >> during active frame. >> + */ >> + if (HAS_DC3CO(display) && > We can do away with HAS_DC3CO and just use the intel_display_wa framework > Check intel_display_wa.c intel_display_wa.h as reference. > > Agreed,will add14026643300 to the intel_display_wa framework and use that here. >> + !intel_dp->psr.panel_replay_enabled && >> + !intel_dp->psr.su_region_et_enabled) >> + intel_de_rmw(display, XE3LPD_CHICKEN_DCPR_4, >> + 0, DCPR4_BLOCK_DC3CO_ACTIVE_FRAME); >> } >> >> /* Wa_16025596647 */ >> @@ -2344,6 +2356,10 @@ static void intel_psr_disable_locked(struct intel_dp >> *intel_dp) >> else if (display->platform.alderlake_p) >> intel_de_rmw(display, CLKGATE_DIS_MISC, >> CLKGATE_DIS_MISC_DMASC_GATING_DIS, >> 0); >> + >> + if (HAS_DC3CO(display)) >> + intel_de_rmw(display, XE3LPD_CHICKEN_DCPR_4, >> + DCPR4_BLOCK_DC3CO_ACTIVE_FRAME, 0); > Ditto. > > Regards, > Suraj Kandpal > >> } >> >> if (intel_dp_is_edp(intel_dp)) >> -- >> 2.43.0