[PATCH 1/2] drm/i915/color: Add 3D LUT to color pipeline since Lunar Lake.

[PATCH 1/2] drm/i915/color: Add 3D LUT to color pipeline since Lunar Lake.

[Austin Hu]

Verified on PTL, where IGT case kms_color_pipeline passes for PipeA
and PipeB.

Signed-off-by: Austin Hu <austin.hu@intel.com>
---
 drivers/gpu/drm/i915/display/intel_color_pipeline.c | 5 ++---
 drivers/gpu/drm/i915/display/intel_display_device.c | 6 ++++++
 drivers/gpu/drm/i915/display/intel_display_device.h | 2 ++
 drivers/gpu/drm/i915/display/intel_display_regs.h   | 1 +
 4 files changed, 11 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_color_pipeline.c b/drivers/gpu/drm/i915/display/intel_color_pipeline.c
index 04af552b3..d26b0f134 100644
--- a/drivers/gpu/drm/i915/display/intel_color_pipeline.c
+++ b/drivers/gpu/drm/i915/display/intel_color_pipeline.c
@@ -47,9 +47,8 @@ int _intel_color_pipeline_plane_init(struct drm_plane *plane, struct drm_prop_en
 	drm_colorop_set_next_property(prev_op, &colorop->base);
 	prev_op = &colorop->base;
 
-	if (DISPLAY_VER(display) >= 35 &&
-	    intel_color_crtc_has_3dlut(display, pipe) &&
-	    plane->type == DRM_PLANE_TYPE_PRIMARY) {
+	if ((DISPLAY_VER(display) >= 15) && HAS_3D_LUT(display) &&
+			intel_color_crtc_has_3dlut(display, pipe)) {
 		colorop = intel_colorop_create(INTEL_PLANE_CB_3DLUT);
 
 		ret = drm_plane_colorop_3dlut_init(dev, &colorop->base, plane, 17,
diff --git a/drivers/gpu/drm/i915/display/intel_display_device.c b/drivers/gpu/drm/i915/display/intel_display_device.c
index 1170afaa8..765fd08df 100644
--- a/drivers/gpu/drm/i915/display/intel_display_device.c
+++ b/drivers/gpu/drm/i915/display/intel_display_device.c
@@ -1903,6 +1903,12 @@ static void __intel_display_device_info_runtime_init(struct intel_display *displ
 				if (display_runtime->num_scalers[pipe])
 					display_runtime->num_scalers[pipe] = 1;
 		}
+
+		if (REG_FIELD_GET(XE2LPD_DE_CAP_3DLUT_MASK, cap) ==
+		    XE2LPD_DE_CAP_3DLUT_REMOVED)
+			display_runtime->has_3d_lut = false;
+		else
+			display_runtime->has_3d_lut = true;
 	}
 
 	if (DISPLAY_VER(display) >= 30)
diff --git a/drivers/gpu/drm/i915/display/intel_display_device.h b/drivers/gpu/drm/i915/display/intel_display_device.h
index b559ef43d..1dc24a86b 100644
--- a/drivers/gpu/drm/i915/display/intel_display_device.h
+++ b/drivers/gpu/drm/i915/display/intel_display_device.h
@@ -171,6 +171,7 @@ struct intel_display_platforms {
 #define HAS_DSC(__display)		(DISPLAY_RUNTIME_INFO(__display)->has_dsc)
 #define HAS_DSC_3ENGINES(__display)	(DISPLAY_VERx100(__display) == 1401 && HAS_DSC(__display))
 #define HAS_DSC_MST(__display)		(DISPLAY_VER(__display) >= 12 && HAS_DSC(__display))
+#define HAS_3D_LUT(__display)		(DISPLAY_RUNTIME_INFO(__display)->has_3d_lut)
 #define HAS_FBC(__display)		(DISPLAY_RUNTIME_INFO(__display)->fbc_mask != 0)
 #define HAS_FBC_DIRTY_RECT(__display)	(DISPLAY_VER(__display) >= 30)
 #define HAS_FPGA_DBG_UNCLAIMED(__display)	(DISPLAY_INFO(__display)->has_fpga_dbg)
@@ -277,6 +278,7 @@ struct intel_display_runtime_info {
 	bool has_hdcp;
 	bool has_dmc;
 	bool has_dsc;
+	bool has_3d_lut;
 	bool edp_typec_support;
 	bool has_dbuf_overlap_detection;
 };
diff --git a/drivers/gpu/drm/i915/display/intel_display_regs.h b/drivers/gpu/drm/i915/display/intel_display_regs.h
index 9d71e26a4..016bd2846 100644
--- a/drivers/gpu/drm/i915/display/intel_display_regs.h
+++ b/drivers/gpu/drm/i915/display/intel_display_regs.h
@@ -1538,6 +1538,7 @@
 
 #define XE2LPD_DE_CAP			_MMIO(0x41100)
 #define   XE2LPD_DE_CAP_3DLUT_MASK	REG_GENMASK(31, 30)
+#define   XE2LPD_DE_CAP_3DLUT_REMOVED	1
 #define   XE2LPD_DE_CAP_DSC_MASK	REG_GENMASK(29, 28)
 #define   XE2LPD_DE_CAP_DSC_REMOVED	1
 #define   XE2LPD_DE_CAP_SCALER_MASK	REG_GENMASK(27, 26)
-- 
2.34.1

[PATCH 2/2] drm/i915/color: Attach the 3D LUT block to required DE Plane.

[Austin Hu]

Or attach to Pipe directly for the unsupported Plane(s).

Signed-off-by: Austin Hu <austin.hu@intel.com>
---
 drivers/gpu/drm/i915/display/intel_color.c    | 29 ++++++++++++++++---
 drivers/gpu/drm/i915/display/intel_color.h    | 11 ++-----
 drivers/gpu/drm/i915/display/intel_plane.c    |  4 +--
 .../drm/i915/display/skl_universal_plane.c    |  2 +-
 4 files changed, 30 insertions(+), 16 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_color.c b/drivers/gpu/drm/i915/display/intel_color.c
index e79506554..dff33c9c1 100644
--- a/drivers/gpu/drm/i915/display/intel_color.c
+++ b/drivers/gpu/drm/i915/display/intel_color.c
@@ -4090,7 +4090,10 @@ static void glk_load_lut_3d(struct intel_dsb *dsb,
 	intel_de_write_dsb(display, dsb, LUT_3D_INDEX(pipe), 0);
 }
 
-static void glk_lut_3d_commit(struct intel_dsb *dsb, struct intel_crtc *crtc, bool enable)
+static void glk_lut_3d_commit(struct intel_dsb *dsb,
+		struct intel_crtc *crtc,
+		struct intel_plane *plane,
+		bool enable)
 {
 	struct intel_display *display = to_intel_display(crtc);
 	enum pipe pipe = crtc->pipe;
@@ -4102,8 +4105,25 @@ static void glk_lut_3d_commit(struct intel_dsb *dsb, struct intel_crtc *crtc, bo
 		return;
 	}
 
-	if (enable)
-		val = LUT_3D_ENABLE | LUT_3D_READY | LUT_3D_BIND_PLANE_1;
+	if (enable) {
+		val = LUT_3D_ENABLE | LUT_3D_READY;
+
+		switch (plane->id) {
+		case PLANE_1:
+			val |= LUT_3D_BIND_PLANE_1;
+			break;
+		case PLANE_2:
+			val |= LUT_3D_BIND_PLANE_2;
+			break;
+		case PLANE_3:
+			val |= LUT_3D_BIND_PLANE_3;
+			break;
+		default:
+			/* Attached the 3D LUT block to Pipe. */
+			val |= LUT_3D_BIND_PIPE;
+			break;
+		}
+	}
 
 	intel_de_write_dsb(display, dsb, LUT_3D_CTL(pipe), val);
 }
@@ -4238,13 +4258,14 @@ static const struct intel_color_funcs ilk_color_funcs = {
 };
 
 void intel_color_plane_commit_arm(struct intel_dsb *dsb,
+				  struct intel_plane *plane,
 				  const struct intel_plane_state *plane_state)
 {
 	struct intel_display *display = to_intel_display(plane_state);
 	struct intel_crtc *crtc = to_intel_crtc(plane_state->uapi.crtc);
 
 	if (crtc && intel_color_crtc_has_3dlut(display, crtc->pipe))
-		glk_lut_3d_commit(dsb, crtc, !!plane_state->hw.lut_3d);
+		glk_lut_3d_commit(dsb, crtc, plane, !!plane_state->hw.lut_3d);
 }
 
 static void
diff --git a/drivers/gpu/drm/i915/display/intel_color.h b/drivers/gpu/drm/i915/display/intel_color.h
index c21b9bdf7..bc8192d75 100644
--- a/drivers/gpu/drm/i915/display/intel_color.h
+++ b/drivers/gpu/drm/i915/display/intel_color.h
@@ -7,15 +7,7 @@
 #define __INTEL_COLOR_H__
 
 #include <linux/types.h>
-
-struct intel_atomic_state;
-struct intel_crtc_state;
-struct intel_crtc;
-struct intel_display;
-struct intel_dsb;
-struct intel_plane_state;
-struct drm_property_blob;
-enum pipe;
+#include "intel_display_types.h"
 
 void intel_color_init_hooks(struct intel_display *display);
 int intel_color_init(struct intel_display *display);
@@ -45,6 +37,7 @@ void intel_color_assert_luts(const struct intel_crtc_state *crtc_state);
 void intel_color_plane_program_pipeline(struct intel_dsb *dsb,
 					const struct intel_plane_state *plane_state);
 void intel_color_plane_commit_arm(struct intel_dsb *dsb,
+				  struct intel_plane *plane,
 				  const struct intel_plane_state *plane_state);
 bool intel_color_crtc_has_3dlut(struct intel_display *display, enum pipe pipe);
 #endif /* __INTEL_COLOR_H__ */
diff --git a/drivers/gpu/drm/i915/display/intel_plane.c b/drivers/gpu/drm/i915/display/intel_plane.c
index ab6a58530..305e8e60f 100644
--- a/drivers/gpu/drm/i915/display/intel_plane.c
+++ b/drivers/gpu/drm/i915/display/intel_plane.c
@@ -345,11 +345,11 @@ intel_plane_colorop_replace_blob(struct intel_plane_state *plane_state,
 	if (intel_colorop->id == INTEL_PLANE_CB_CSC)
 		return drm_property_replace_blob(&plane_state->hw.ctm, blob);
 	else if (intel_colorop->id == INTEL_PLANE_CB_PRE_CSC_LUT)
-		return	drm_property_replace_blob(&plane_state->hw.degamma_lut, blob);
+		return drm_property_replace_blob(&plane_state->hw.degamma_lut, blob);
 	else if (intel_colorop->id == INTEL_PLANE_CB_POST_CSC_LUT)
 		return drm_property_replace_blob(&plane_state->hw.gamma_lut, blob);
 	else if (intel_colorop->id == INTEL_PLANE_CB_3DLUT)
-		return	drm_property_replace_blob(&plane_state->hw.lut_3d, blob);
+		return drm_property_replace_blob(&plane_state->hw.lut_3d, blob);
 
 	return false;
 }
diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane.c b/drivers/gpu/drm/i915/display/skl_universal_plane.c
index ee8e24497..b68e222c3 100644
--- a/drivers/gpu/drm/i915/display/skl_universal_plane.c
+++ b/drivers/gpu/drm/i915/display/skl_universal_plane.c
@@ -1673,7 +1673,7 @@ icl_plane_update_arm(struct intel_dsb *dsb,
 
 	icl_plane_update_sel_fetch_arm(dsb, plane, crtc_state, plane_state);
 
-	intel_color_plane_commit_arm(dsb, plane_state);
+	intel_color_plane_commit_arm(dsb, plane, plane_state);
 
 	/*
 	 * In order to have FBC for fp16 formats pixel normalizer block must be
-- 
2.34.1

Re: [PATCH 1/2] drm/i915/color: Add 3D LUT to color pipeline since Lunar Lake.

[Jani Nikula]

On Fri, 06 Feb 2026, Austin Hu <austin.hu@intel.com> wrote:
> Verified on PTL, where IGT case kms_color_pipeline passes for PipeA
> and PipeB.
>
> Signed-off-by: Austin Hu <austin.hu@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_color_pipeline.c | 5 ++---
>  drivers/gpu/drm/i915/display/intel_display_device.c | 6 ++++++
>  drivers/gpu/drm/i915/display/intel_display_device.h | 2 ++
>  drivers/gpu/drm/i915/display/intel_display_regs.h   | 1 +
>  4 files changed, 11 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_color_pipeline.c b/drivers/gpu/drm/i915/display/intel_color_pipeline.c
> index 04af552b3..d26b0f134 100644
> --- a/drivers/gpu/drm/i915/display/intel_color_pipeline.c
> +++ b/drivers/gpu/drm/i915/display/intel_color_pipeline.c
> @@ -47,9 +47,8 @@ int _intel_color_pipeline_plane_init(struct drm_plane *plane, struct drm_prop_en
>  	drm_colorop_set_next_property(prev_op, &colorop->base);
>  	prev_op = &colorop->base;
>  
> -	if (DISPLAY_VER(display) >= 35 &&
> -	    intel_color_crtc_has_3dlut(display, pipe) &&
> -	    plane->type == DRM_PLANE_TYPE_PRIMARY) {
> +	if ((DISPLAY_VER(display) >= 15) && HAS_3D_LUT(display) &&
> +			intel_color_crtc_has_3dlut(display, pipe)) {

intel_color_crtc_has_3dlut() should have the check for
HAS_3D_LUT(). Basically:

	if (HAS_3D_LUT())
		return pipe == PIPE_A || pipe == PIPE_B;
	else
		return false;

>  		colorop = intel_colorop_create(INTEL_PLANE_CB_3DLUT);
>  
>  		ret = drm_plane_colorop_3dlut_init(dev, &colorop->base, plane, 17,
> diff --git a/drivers/gpu/drm/i915/display/intel_display_device.c b/drivers/gpu/drm/i915/display/intel_display_device.c
> index 1170afaa8..765fd08df 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_device.c
> +++ b/drivers/gpu/drm/i915/display/intel_display_device.c
> @@ -1903,6 +1903,12 @@ static void __intel_display_device_info_runtime_init(struct intel_display *displ
>  				if (display_runtime->num_scalers[pipe])
>  					display_runtime->num_scalers[pipe] = 1;
>  		}
> +
> +		if (REG_FIELD_GET(XE2LPD_DE_CAP_3DLUT_MASK, cap) ==
> +		    XE2LPD_DE_CAP_3DLUT_REMOVED)
> +			display_runtime->has_3d_lut = false;
> +		else
> +			display_runtime->has_3d_lut = true;

This won't work.

You'll need to initialize .has_3d_lut on the platforms that have it in
.__runtime_defaults.has_3d_lut. We can't have multiple truths for
whether a platform has a feature or not.

Initially, that means replacing the DISPLAY_VER(display) >= 12 check in
intel_color_crtc_has_3dlut() with .has_3d_lut. It could be a separate
patch.

Then disable the runtime value based on the capability.

BR,
Jani.

>  	}
>  
>  	if (DISPLAY_VER(display) >= 30)
> diff --git a/drivers/gpu/drm/i915/display/intel_display_device.h b/drivers/gpu/drm/i915/display/intel_display_device.h
> index b559ef43d..1dc24a86b 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_device.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_device.h
> @@ -171,6 +171,7 @@ struct intel_display_platforms {
>  #define HAS_DSC(__display)		(DISPLAY_RUNTIME_INFO(__display)->has_dsc)
>  #define HAS_DSC_3ENGINES(__display)	(DISPLAY_VERx100(__display) == 1401 && HAS_DSC(__display))
>  #define HAS_DSC_MST(__display)		(DISPLAY_VER(__display) >= 12 && HAS_DSC(__display))
> +#define HAS_3D_LUT(__display)		(DISPLAY_RUNTIME_INFO(__display)->has_3d_lut)
>  #define HAS_FBC(__display)		(DISPLAY_RUNTIME_INFO(__display)->fbc_mask != 0)
>  #define HAS_FBC_DIRTY_RECT(__display)	(DISPLAY_VER(__display) >= 30)
>  #define HAS_FPGA_DBG_UNCLAIMED(__display)	(DISPLAY_INFO(__display)->has_fpga_dbg)
> @@ -277,6 +278,7 @@ struct intel_display_runtime_info {
>  	bool has_hdcp;
>  	bool has_dmc;
>  	bool has_dsc;
> +	bool has_3d_lut;
>  	bool edp_typec_support;
>  	bool has_dbuf_overlap_detection;
>  };
> diff --git a/drivers/gpu/drm/i915/display/intel_display_regs.h b/drivers/gpu/drm/i915/display/intel_display_regs.h
> index 9d71e26a4..016bd2846 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_regs.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_regs.h
> @@ -1538,6 +1538,7 @@
>  
>  #define XE2LPD_DE_CAP			_MMIO(0x41100)
>  #define   XE2LPD_DE_CAP_3DLUT_MASK	REG_GENMASK(31, 30)
> +#define   XE2LPD_DE_CAP_3DLUT_REMOVED	1
>  #define   XE2LPD_DE_CAP_DSC_MASK	REG_GENMASK(29, 28)
>  #define   XE2LPD_DE_CAP_DSC_REMOVED	1
>  #define   XE2LPD_DE_CAP_SCALER_MASK	REG_GENMASK(27, 26)

-- 
Jani Nikula, Intel

Re: [PATCH 1/2] drm/i915/color: Add 3D LUT to color pipeline since Lunar Lake.

[Jani Nikula]

On Fri, 06 Feb 2026, Austin Hu <austin.hu@intel.com> wrote:
> Verified on PTL, where IGT case kms_color_pipeline passes for PipeA
> and PipeB.

PS. The Subject should be a short description of the "what". But that
subject does not really match what the patch does. Probably the patch
needs to be split to handle adding the .has_3d_lut and fusing in one
patch, and expanding the platforms separately.

The commit message itself should expand on the "what", and include a
"why". The details about verification and IGT are less relevant, and
certainly that should not be the only part of the commit message.

BR,
Jani.

>
> Signed-off-by: Austin Hu <austin.hu@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_color_pipeline.c | 5 ++---
>  drivers/gpu/drm/i915/display/intel_display_device.c | 6 ++++++
>  drivers/gpu/drm/i915/display/intel_display_device.h | 2 ++
>  drivers/gpu/drm/i915/display/intel_display_regs.h   | 1 +
>  4 files changed, 11 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_color_pipeline.c b/drivers/gpu/drm/i915/display/intel_color_pipeline.c
> index 04af552b3..d26b0f134 100644
> --- a/drivers/gpu/drm/i915/display/intel_color_pipeline.c
> +++ b/drivers/gpu/drm/i915/display/intel_color_pipeline.c
> @@ -47,9 +47,8 @@ int _intel_color_pipeline_plane_init(struct drm_plane *plane, struct drm_prop_en
>  	drm_colorop_set_next_property(prev_op, &colorop->base);
>  	prev_op = &colorop->base;
>  
> -	if (DISPLAY_VER(display) >= 35 &&
> -	    intel_color_crtc_has_3dlut(display, pipe) &&
> -	    plane->type == DRM_PLANE_TYPE_PRIMARY) {
> +	if ((DISPLAY_VER(display) >= 15) && HAS_3D_LUT(display) &&
> +			intel_color_crtc_has_3dlut(display, pipe)) {
>  		colorop = intel_colorop_create(INTEL_PLANE_CB_3DLUT);
>  
>  		ret = drm_plane_colorop_3dlut_init(dev, &colorop->base, plane, 17,
> diff --git a/drivers/gpu/drm/i915/display/intel_display_device.c b/drivers/gpu/drm/i915/display/intel_display_device.c
> index 1170afaa8..765fd08df 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_device.c
> +++ b/drivers/gpu/drm/i915/display/intel_display_device.c
> @@ -1903,6 +1903,12 @@ static void __intel_display_device_info_runtime_init(struct intel_display *displ
>  				if (display_runtime->num_scalers[pipe])
>  					display_runtime->num_scalers[pipe] = 1;
>  		}
> +
> +		if (REG_FIELD_GET(XE2LPD_DE_CAP_3DLUT_MASK, cap) ==
> +		    XE2LPD_DE_CAP_3DLUT_REMOVED)
> +			display_runtime->has_3d_lut = false;
> +		else
> +			display_runtime->has_3d_lut = true;
>  	}
>  
>  	if (DISPLAY_VER(display) >= 30)
> diff --git a/drivers/gpu/drm/i915/display/intel_display_device.h b/drivers/gpu/drm/i915/display/intel_display_device.h
> index b559ef43d..1dc24a86b 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_device.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_device.h
> @@ -171,6 +171,7 @@ struct intel_display_platforms {
>  #define HAS_DSC(__display)		(DISPLAY_RUNTIME_INFO(__display)->has_dsc)
>  #define HAS_DSC_3ENGINES(__display)	(DISPLAY_VERx100(__display) == 1401 && HAS_DSC(__display))
>  #define HAS_DSC_MST(__display)		(DISPLAY_VER(__display) >= 12 && HAS_DSC(__display))
> +#define HAS_3D_LUT(__display)		(DISPLAY_RUNTIME_INFO(__display)->has_3d_lut)
>  #define HAS_FBC(__display)		(DISPLAY_RUNTIME_INFO(__display)->fbc_mask != 0)
>  #define HAS_FBC_DIRTY_RECT(__display)	(DISPLAY_VER(__display) >= 30)
>  #define HAS_FPGA_DBG_UNCLAIMED(__display)	(DISPLAY_INFO(__display)->has_fpga_dbg)
> @@ -277,6 +278,7 @@ struct intel_display_runtime_info {
>  	bool has_hdcp;
>  	bool has_dmc;
>  	bool has_dsc;
> +	bool has_3d_lut;
>  	bool edp_typec_support;
>  	bool has_dbuf_overlap_detection;
>  };
> diff --git a/drivers/gpu/drm/i915/display/intel_display_regs.h b/drivers/gpu/drm/i915/display/intel_display_regs.h
> index 9d71e26a4..016bd2846 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_regs.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_regs.h
> @@ -1538,6 +1538,7 @@
>  
>  #define XE2LPD_DE_CAP			_MMIO(0x41100)
>  #define   XE2LPD_DE_CAP_3DLUT_MASK	REG_GENMASK(31, 30)
> +#define   XE2LPD_DE_CAP_3DLUT_REMOVED	1
>  #define   XE2LPD_DE_CAP_DSC_MASK	REG_GENMASK(29, 28)
>  #define   XE2LPD_DE_CAP_DSC_REMOVED	1
>  #define   XE2LPD_DE_CAP_SCALER_MASK	REG_GENMASK(27, 26)

-- 
Jani Nikula, Intel

Re: [PATCH 2/2] drm/i915/color: Attach the 3D LUT block to required DE Plane.

[Jani Nikula]

On Fri, 06 Feb 2026, Austin Hu <austin.hu@intel.com> wrote:
> Or attach to Pipe directly for the unsupported Plane(s).

Insufficient commit message. Please don't add a period at the end of the
subject.

>
> Signed-off-by: Austin Hu <austin.hu@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_color.c    | 29 ++++++++++++++++---
>  drivers/gpu/drm/i915/display/intel_color.h    | 11 ++-----
>  drivers/gpu/drm/i915/display/intel_plane.c    |  4 +--
>  .../drm/i915/display/skl_universal_plane.c    |  2 +-
>  4 files changed, 30 insertions(+), 16 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_color.c b/drivers/gpu/drm/i915/display/intel_color.c
> index e79506554..dff33c9c1 100644
> --- a/drivers/gpu/drm/i915/display/intel_color.c
> +++ b/drivers/gpu/drm/i915/display/intel_color.c
> @@ -4090,7 +4090,10 @@ static void glk_load_lut_3d(struct intel_dsb *dsb,
>  	intel_de_write_dsb(display, dsb, LUT_3D_INDEX(pipe), 0);
>  }
>  
> -static void glk_lut_3d_commit(struct intel_dsb *dsb, struct intel_crtc *crtc, bool enable)
> +static void glk_lut_3d_commit(struct intel_dsb *dsb,
> +		struct intel_crtc *crtc,
> +		struct intel_plane *plane,
> +		bool enable)

Please fix the indentation, that's not a style used anywhere.

>  {
>  	struct intel_display *display = to_intel_display(crtc);
>  	enum pipe pipe = crtc->pipe;
> @@ -4102,8 +4105,25 @@ static void glk_lut_3d_commit(struct intel_dsb *dsb, struct intel_crtc *crtc, bo
>  		return;
>  	}
>  
> -	if (enable)
> -		val = LUT_3D_ENABLE | LUT_3D_READY | LUT_3D_BIND_PLANE_1;
> +	if (enable) {
> +		val = LUT_3D_ENABLE | LUT_3D_READY;
> +
> +		switch (plane->id) {
> +		case PLANE_1:
> +			val |= LUT_3D_BIND_PLANE_1;
> +			break;
> +		case PLANE_2:
> +			val |= LUT_3D_BIND_PLANE_2;
> +			break;
> +		case PLANE_3:
> +			val |= LUT_3D_BIND_PLANE_3;
> +			break;
> +		default:
> +			/* Attached the 3D LUT block to Pipe. */

Attached? Or Attach? There's no need to capitalize pipe.

> +			val |= LUT_3D_BIND_PIPE;
> +			break;
> +		}
> +	}
>  
>  	intel_de_write_dsb(display, dsb, LUT_3D_CTL(pipe), val);
>  }
> @@ -4238,13 +4258,14 @@ static const struct intel_color_funcs ilk_color_funcs = {
>  };
>  
>  void intel_color_plane_commit_arm(struct intel_dsb *dsb,
> +				  struct intel_plane *plane,
>  				  const struct intel_plane_state *plane_state)
>  {
>  	struct intel_display *display = to_intel_display(plane_state);
>  	struct intel_crtc *crtc = to_intel_crtc(plane_state->uapi.crtc);
>  
>  	if (crtc && intel_color_crtc_has_3dlut(display, crtc->pipe))
> -		glk_lut_3d_commit(dsb, crtc, !!plane_state->hw.lut_3d);
> +		glk_lut_3d_commit(dsb, crtc, plane, !!plane_state->hw.lut_3d);

Just pass plane_state, and figure the rest out from that.

	struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);

>  }
>  
>  static void
> diff --git a/drivers/gpu/drm/i915/display/intel_color.h b/drivers/gpu/drm/i915/display/intel_color.h
> index c21b9bdf7..bc8192d75 100644
> --- a/drivers/gpu/drm/i915/display/intel_color.h
> +++ b/drivers/gpu/drm/i915/display/intel_color.h
> @@ -7,15 +7,7 @@
>  #define __INTEL_COLOR_H__
>  
>  #include <linux/types.h>
> -
> -struct intel_atomic_state;
> -struct intel_crtc_state;
> -struct intel_crtc;
> -struct intel_display;
> -struct intel_dsb;
> -struct intel_plane_state;
> -struct drm_property_blob;
> -enum pipe;
> +#include "intel_display_types.h"

Absolutely not.

Please never include header from headers unless you absolutely have
to. Use forward declarations instead.

We've put a lot of effort into reducing header interdependencies, which
improves incremental build times quite nicely.

Here, it would be sufficient to add

struct intel_plane;

forward declaration, *except* you can get the plane from the plane state
with no changes in the API:

	struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);

>  void intel_color_init_hooks(struct intel_display *display);
>  int intel_color_init(struct intel_display *display);
> @@ -45,6 +37,7 @@ void intel_color_assert_luts(const struct intel_crtc_state *crtc_state);
>  void intel_color_plane_program_pipeline(struct intel_dsb *dsb,
>  					const struct intel_plane_state *plane_state);
>  void intel_color_plane_commit_arm(struct intel_dsb *dsb,
> +				  struct intel_plane *plane,
>  				  const struct intel_plane_state *plane_state);
>  bool intel_color_crtc_has_3dlut(struct intel_display *display, enum pipe pipe);
>  #endif /* __INTEL_COLOR_H__ */
> diff --git a/drivers/gpu/drm/i915/display/intel_plane.c b/drivers/gpu/drm/i915/display/intel_plane.c
> index ab6a58530..305e8e60f 100644
> --- a/drivers/gpu/drm/i915/display/intel_plane.c
> +++ b/drivers/gpu/drm/i915/display/intel_plane.c
> @@ -345,11 +345,11 @@ intel_plane_colorop_replace_blob(struct intel_plane_state *plane_state,
>  	if (intel_colorop->id == INTEL_PLANE_CB_CSC)
>  		return drm_property_replace_blob(&plane_state->hw.ctm, blob);
>  	else if (intel_colorop->id == INTEL_PLANE_CB_PRE_CSC_LUT)
> -		return	drm_property_replace_blob(&plane_state->hw.degamma_lut, blob);
> +		return drm_property_replace_blob(&plane_state->hw.degamma_lut, blob);
>  	else if (intel_colorop->id == INTEL_PLANE_CB_POST_CSC_LUT)
>  		return drm_property_replace_blob(&plane_state->hw.gamma_lut, blob);
>  	else if (intel_colorop->id == INTEL_PLANE_CB_3DLUT)
> -		return	drm_property_replace_blob(&plane_state->hw.lut_3d, blob);
> +		return drm_property_replace_blob(&plane_state->hw.lut_3d, blob);

Unrelated changes that don't belong in this patch.

>  
>  	return false;
>  }
> diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane.c b/drivers/gpu/drm/i915/display/skl_universal_plane.c
> index ee8e24497..b68e222c3 100644
> --- a/drivers/gpu/drm/i915/display/skl_universal_plane.c
> +++ b/drivers/gpu/drm/i915/display/skl_universal_plane.c
> @@ -1673,7 +1673,7 @@ icl_plane_update_arm(struct intel_dsb *dsb,
>  
>  	icl_plane_update_sel_fetch_arm(dsb, plane, crtc_state, plane_state);
>  
> -	intel_color_plane_commit_arm(dsb, plane_state);
> +	intel_color_plane_commit_arm(dsb, plane, plane_state);
>  
>  	/*
>  	 * In order to have FBC for fp16 formats pixel normalizer block must be

-- 
Jani Nikula, Intel