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X-MS-Exchange-CrossTenant-OriginalArrivalTime: 06 Jul 2026 12:00:17.7770 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 46c98d88-e344-4ed4-8496-4ed7712e255d X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: 1o5OKltgmeLCYxdjuf77Z/W8UMvX2TYTMYOtrV3QhBVmX0V9TyAy/kKTGIKYTTJb650Aj7Q5u7P0fMbkTft+PocnY+1YuJG3eGxkjHd670U= X-MS-Exchange-Transport-CrossTenantHeadersStamped: IA1PR11MB6370 X-OriginatorOrg: intel.com X-BeenThere: intel-xe@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel Xe graphics driver List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-xe-bounces@lists.freedesktop.org Sender: "Intel-xe" On 6/16/2026 8:12 PM, Mitul Golani wrote: > Enable CMRR during compute config and add related state > checker for the same. > > Signed-off-by: Mitul Golani > --- > drivers/gpu/drm/i915/display/intel_vrr.c | 11 +++++++++++ > 1 file changed, 11 insertions(+) > > diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c > index 2d5f0f17bf3c..9ef559195c68 100644 > --- a/drivers/gpu/drm/i915/display/intel_vrr.c > +++ b/drivers/gpu/drm/i915/display/intel_vrr.c > @@ -285,6 +285,8 @@ intel_vrr_cmrr_compute_config(struct intel_crtc_state *crtc_state) > adjusted_pixel_rate = mul_u32_u32(adjusted_mode->crtc_clock, 1000) * multiplier_n; > crtc_state->vrr.cmrr.cmrr_m = do_div(adjusted_pixel_rate, crtc_state->vrr.cmrr.cmrr_n); > > + crtc_state->vrr.cmrr.enable = true; > + > return; > } > > @@ -876,6 +878,7 @@ intel_vrr_enable_cmrr(const struct intel_crtc_state *crtc_state) > { > struct intel_display *display = to_intel_display(crtc_state); > enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; > + u32 vrr_ctl = intel_de_read(display, TRANS_VRR_CTL(display, cpu_transcoder)); > > intel_de_write(display, TRANS_CMRR_M_HI(display, cpu_transcoder), > upper_32_bits(crtc_state->vrr.cmrr.cmrr_m)); > @@ -885,6 +888,9 @@ intel_vrr_enable_cmrr(const struct intel_crtc_state *crtc_state) > lower_32_bits(crtc_state->vrr.cmrr.cmrr_n)); > intel_de_write(display, TRANS_CMRR_N_HI(display, cpu_transcoder), > upper_32_bits(crtc_state->vrr.cmrr.cmrr_n)); > + > + vrr_ctl |= VRR_CTL_CMRR_ENABLE; > + intel_de_write(display, TRANS_VRR_CTL(display, cpu_transcoder), vrr_ctl); This patch should only enable the feature. It should not add any new programming, previous patches should already handle them. Bspec states that "TRANS_CMRR_N_HI register should be written last in this sequence of CMRR register writes." Please confirm if it also includes CMRR enable bit in TRANS_VRR_CTL. Also, this is still true from v1 : "The target rr divider bit is always set to true in intel_dp_compute_as_sdp(). This is wrong for non-video mode refresh rates." Please add change log in commit messages wherever applicable. == Chaitanya > } > > static void > @@ -892,11 +898,15 @@ intel_vrr_disable_cmrr(const struct intel_crtc_state *crtc_state) > { > struct intel_display *display = to_intel_display(crtc_state); > enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; > + u32 vrr_ctl = intel_de_read(display, TRANS_VRR_CTL(display, cpu_transcoder)); > > intel_de_write(display, TRANS_CMRR_M_HI(display, cpu_transcoder), 0); > intel_de_write(display, TRANS_CMRR_M_LO(display, cpu_transcoder), 0); > intel_de_write(display, TRANS_CMRR_N_LO(display, cpu_transcoder), 0); > intel_de_write(display, TRANS_CMRR_N_HI(display, cpu_transcoder), 0); > + > + vrr_ctl &= ~VRR_CTL_CMRR_ENABLE; > + intel_de_write(display, TRANS_VRR_CTL(display, cpu_transcoder), vrr_ctl); > } > > static void > @@ -1138,6 +1148,7 @@ void intel_vrr_get_config(struct intel_crtc_state *crtc_state) > TRANS_VRR_CTL(display, cpu_transcoder)); > > if (HAS_CMRR(display)) { > + crtc_state->vrr.cmrr.enable = trans_vrr_ctl & VRR_CTL_CMRR_ENABLE; > crtc_state->vrr.cmrr.cmrr_n = > intel_de_read64_2x32(display, TRANS_CMRR_N_LO(display, cpu_transcoder)); > crtc_state->vrr.cmrr.cmrr_m =