Re: [v6 2/9] drm/i915/color: Add CSC on SDR plane color pipeline

["Borah, Chaitanya Kumar" <chaitanya.kumar.borah@intel.com>]

Hello Uma,

On 8/4/2026 6:01 PM, Chaitanya Kumar Borah wrote:
> Add the fixed-function CSC block to color pipeline in SDR planes
> as a DRM_COLOROP_FIXED_MATRIX colorop.
> 
> v2:
> - s/DRM_COLOROP_FM_YCBCR2020_FULL_RGB_NC/
> 	DRM_COLOROP_FM_YCBCR2020_NC_FULL_RGB
> - Inline icl_is_hdr_plane() instead of storing in local variable
> 
> v3:
> - In preparation of a simple pipeline
> 	[YUV Full/Limited -> RGB]
>    Make the Fixed Matrix ColorOp support Limited Range enums
>    (DRM_COLOROP_FM_YCBCRXXX_LIMITED_RGB) too.
> - Therefore s/sdr_plane_pipeline/sdr_plane_yuv_pipeline
> 
> Signed-off-by: Chaitanya Kumar Borah <chaitanya.kumar.borah@intel.com>
> Reviewed-by: Uma Shankar <uma.shankar@intel.com> #v2

Can I consider your RB for v3 too?

==
Chaitanya

> ---
>   .../drm/i915/display/intel_color_pipeline.c   | 23 ++++++++++++++++++-
>   .../drm/i915/display/intel_display_limits.h   |  1 +
>   2 files changed, 23 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_color_pipeline.c b/drivers/gpu/drm/i915/display/intel_color_pipeline.c
> index 6cf8080ee800..efd4375c4331 100644
> --- a/drivers/gpu/drm/i915/display/intel_color_pipeline.c
> +++ b/drivers/gpu/drm/i915/display/intel_color_pipeline.c
> @@ -43,6 +43,18 @@ static const enum intel_color_block hdr_plane_pipeline[] = {
>   	INTEL_PLANE_CB_POST_CSC_LUT,
>   };
>   
> +static const enum intel_color_block sdr_plane_yuv_pipeline[] = {
> +	INTEL_PLANE_CB_CSC_FF,
> +};
> +
> +static const u64 intel_plane_supported_csc_ff =
> +		BIT(DRM_COLOROP_FM_YCBCR601_FULL_RGB) |
> +		BIT(DRM_COLOROP_FM_YCBCR601_LIMITED_RGB) |
> +		BIT(DRM_COLOROP_FM_YCBCR709_FULL_RGB) |
> +		BIT(DRM_COLOROP_FM_YCBCR709_LIMITED_RGB) |
> +		BIT(DRM_COLOROP_FM_YCBCR2020_NC_FULL_RGB) |
> +		BIT(DRM_COLOROP_FM_YCBCR2020_NC_LIMITED_RGB);
> +
>   static bool plane_has_3dlut(struct intel_display *display, enum pipe pipe,
>   			    struct drm_plane *plane)
>   {
> @@ -92,6 +104,12 @@ struct intel_colorop *intel_color_pipeline_plane_add_colorop(struct drm_plane *p
>   							  DRM_COLOROP_LUT1D_INTERPOLATION_LINEAR,
>   							  DRM_COLOROP_FLAG_ALLOW_BYPASS);
>   		break;
> +	case INTEL_PLANE_CB_CSC_FF:
> +		ret = drm_plane_colorop_fixed_matrix_init(dev, &colorop->base, plane,
> +							  &intel_colorop_funcs,
> +							  intel_plane_supported_csc_ff,
> +							  DRM_COLOROP_FLAG_ALLOW_BYPASS);
> +		break;
>   	default:
>   		drm_err(plane->dev, "Invalid colorop id [%d]", id);
>   		ret = -EINVAL;
> @@ -126,9 +144,12 @@ int _intel_color_pipeline_plane_init(struct drm_plane *plane, struct drm_prop_en
>   	if (plane_has_3dlut(display, pipe, plane)) {
>   		pipeline = xe3plpd_primary_plane_pipeline;
>   		pipeline_len = ARRAY_SIZE(xe3plpd_primary_plane_pipeline);
> -	} else {
> +	} else if (icl_is_hdr_plane(display, to_intel_plane(plane)->id)) {
>   		pipeline = hdr_plane_pipeline;
>   		pipeline_len = ARRAY_SIZE(hdr_plane_pipeline);
> +	} else {
> +		pipeline = sdr_plane_yuv_pipeline;
> +		pipeline_len = ARRAY_SIZE(sdr_plane_yuv_pipeline);
>   	}
>   
>   	for (i = 0; i < pipeline_len; i++) {
> diff --git a/drivers/gpu/drm/i915/display/intel_display_limits.h b/drivers/gpu/drm/i915/display/intel_display_limits.h
> index ea89473c177f..7ba7360c574e 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_limits.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_limits.h
> @@ -169,6 +169,7 @@ enum aux_ch {
>   enum intel_color_block {
>   	INTEL_PLANE_CB_PRE_CSC_LUT,
>   	INTEL_PLANE_CB_CSC,
> +	INTEL_PLANE_CB_CSC_FF,
>   	INTEL_PLANE_CB_POST_CSC_LUT,
>   	INTEL_PLANE_CB_3DLUT,
>