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On Fri, Sep 18, 2026, at 21:33, Bjorn Helgaas wrote: > On Thu, May 07, 2026 at 11:14:04PM +0100, Pavel Shirshov wrote: > > The report and the patch below are completely claude'd but the quirk in the patch works. > > > > PCI/ASPM: Intel Battlemage (Arc Pro B70) bricks at boot when > > pcie_aspm.policy=powersupersave enables ASPM_L1.1 on AMD root port link > > I happened on this report that we never responded to. I assume this > is still a problem? > > It looks like it's not a regression, but should still be fixed. > > > ================================================================ > > SUMMARY > > ================================================================ > > > > On Linux 7.0.3, an Intel Arc Pro B70 (Battlemage / BMG-G31, GPU PCI > > ID 8086:e223) plugged into an AMD Ryzen 9 5950X system fails to wake > > from D3cold during PCI core enumeration when the kernel is booted > > with pcie_aspm.policy=powersupersave. The card is permanently > > inaccessible until reboot with a different policy. > > pcie_aspm.policy=powersave (L0s+L1, no substates) works correctly. > > > > The failure surfaces in PCI core first; downstream xe driver bind > > then fails with -EPROTO: > > > > pcieport 0000:02:01.0: Unable to change power state from D3cold > > to D0, device inaccessible > > pcieport 0000:02:02.0: Unable to change power state from D3cold > > to D0, device inaccessible > > xe 0000:03:00.0: Unable to change power state from D3cold to D0, > > device inaccessible > > xe 0000:03:00.0: [drm] Running in SR-IOV VF mode > > [misdetected: dead config space reads as 0xff] > > xe 0000:03:00.0: [drm] *ERROR* VF: Tile0: GT0: Failed to reset > > GuC state (-EPROTO) > > xe 0000:03:00.0: probe with driver xe failed with error -71 > > > > After the brick, "lspci -vvv -s 03:00.0" reports > > "!!! Unknown header type 7f" -- the canonical signature of a PCI > > device whose config space reads return all-ones, i.e. the link to the > > device is dead. > > > > > > ================================================================ > > HARDWARE > > ================================================================ > > > > CPU / root complex: > > AMD Ryzen 9 5950X (Starship/Matisse). The root port hosting the > > BMG card is 0000:00:01.1 -- "Advanced Micro Devices, Inc. [AMD] > > Starship/Matisse GPP Bridge" (subsystem 1022:1453). > > > > GPU: > > Intel Arc Pro B70 -- 8086:e223 (BMG-G31, subsystem 8086:1701). > > > > On-card topology -- the card has a two-layer on-board PCIe switch: > > 0000:01:00.0 Intel 8086:e2ff -- BMG card upstream switch port, > > PCIe 5.0 x16 capable (currently > > downgraded to Gen4 x16). > > 0000:02:01.0 Intel 8086:e2f0 -- BMG card downstream switch > > port, PCIe Gen1 x1 internal. > > 0000:03:00.0 Intel 8086:e223 -- GPU endpoint, PCIe Gen1 x1 > > internal. > > > > Other: > > BIOS has PCIe ASPM enabled in firmware. pcie_aspm=force is NOT > > set on the kernel command line. Motherboard: ASRock X570 > > (specifics in attached dmidecode.txt). > > > > > > ================================================================ > > REPRODUCER > > ================================================================ > > > > Boot any kernel >= 7.0 with kernel command line containing: > > > > pcie_aspm.policy=powersupersave xe.force_probe=* > > > > (Also reproduces under earlier 6.x kernels.) > > > > Reverting the cmdline to "pcie_aspm.policy=powersave" and rebooting > > restores the card. No firmware reset is required between attempts -- > > the brick is purely a runtime link-state failure during kernel boot. > > > > > > ================================================================ > > ASPM NEGOTIATION > > ================================================================ > > > > Captured with "lspci -vvv" on a working policy=powersave boot > > (attached: 20260507-204348-powersave-7.0.3.tar.zst). > > > > Link 1: 00:01.1 AMD root <-> 01:00.0 BMG upstream > > Lower end (AMD root, L1SubCap): > > PCI-PM_L1.2- PCI-PM_L1.1+ ASPM_L1.2- ASPM_L1.1+ > > Upper end (BMG upstream, L1SubCap): > > PCI-PM_L1.2+ PCI-PM_L1.1+ ASPM_L1.2+ ASPM_L1.1+ > > Active L1SubCtl1 under policy=powersave: > > PCI-PM_L1.2- PCI-PM_L1.1- ASPM_L1.2- ASPM_L1.1- > > > > Link 2: 01:00.0 <-> 02:01.0 (card-internal switch) > > No L1SS capability advertised on either end. > > > > Link 3: 02:01.0 <-> 03:00.0 (card-internal to GPU) > > No L1SS capability advertised on either end. > > > > Conclusion: only Link 1 -- the platform-facing AMD<->BMG link -- is > > L1SS-capable on both ends, and the intersection is ASPM_L1.1 only > > (the AMD GPP root port advertises L1.1 but not L1.2). With > > policy=powersupersave, the kernel arms ASPM_L1.1 on this link. After > > that, every D3cold->D0 transition fails. > > > > Both ends advertise multi-retimer support (Retimer+ 2Retimers+ on > > the AMD root port and on the BMG upstream port). Retimers + L1SS > > have a history of wake-recovery problems on other platforms; this > > may be the same class of issue. > > > > > > ================================================================ > > TIMELINE -- failed boot, kernel 7.0.3 > > ================================================================ > > > > Excerpted from dmesg-relevant.txt in the powersupersave capture: > > > > 28.792s pcieport 0000:00:01.1: PME: Signaling with IRQ 48 > > [AMD root port for BMG] > > 28.842s pcieport 0000:02:01.0: Unable to change power state from > > D3cold to D0, device inaccessible > > 28.843s pcieport 0000:02:02.0: Unable to change power state from > > D3cold to D0, device inaccessible > > ... > > 29.034s xe 0000:03:00.0: Unable to change power state from > > D3cold to D0, device inaccessible > > 29.035s xe 0000:03:00.0: [drm] Running in SR-IOV VF mode > > 29.035s xe 0000:03:00.0: [drm] *ERROR* VF: Tile0: GT0: Failed > > to reset GuC state (-EPROTO) > > 29.035s xe 0000:03:00.0: probe with driver xe failed with > > error -71 > > > > The PCI core's first wake attempt at 28.842s (the immediate parent > > bridge of the BMG GPU) fails before any driver probe runs. This > > confirms the failure is in the PCI/ASPM layer, not in xe; xe just > > sees the resulting dead config space and misclassifies the PF as a > > VF. > > > > > > ================================================================ > > WORKING-POLICY LSPCI EXCERPTS (relevant capabilities) > > ================================================================ > > > > policy=powersave baseline, root port 00:01.1: > > > > LnkCap: Speed 16GT/s, Width x16, ASPM L1, Exit Latency L1 <64us > > LnkCtl: ASPM L1 Enabled > > LnkSta: Speed 16GT/s, Width x16 > > Capabilities: [370 v1] L1 PM Substates > > L1SubCap: PCI-PM_L1.2- PCI-PM_L1.1+ ASPM_L1.2- ASPM_L1.1+ > > L1_PM_Substates+ > > L1SubCtl1: PCI-PM_L1.2- PCI-PM_L1.1- ASPM_L1.2- ASPM_L1.1- > > L1SubCtl2: > > > > policy=powersave baseline, BMG upstream 01:00.0: > > > > LnkCap: Speed 32GT/s, Width x16, ASPM L1, Exit Latency L1 <32us > > LnkCtl: ASPM L1 Enabled > > LnkSta: Speed 16GT/s (downgraded), Width x16 > > Capabilities: [244 v1] L1 PM Substates > > L1SubCap: PCI-PM_L1.2+ PCI-PM_L1.1+ ASPM_L1.2+ ASPM_L1.1+ > > L1_PM_Substates+ > > L1SubCtl1: PCI-PM_L1.2- PCI-PM_L1.1- ASPM_L1.2- ASPM_L1.1- > > L1SubCtl2: T_PwrOn=14us > > > > > > ================================================================ > > PROPOSED FIX > > ================================================================ > > > > Disable both L1SS substates on the BMG card's upstream switch port > > (8086:e2ff) via a DECLARE_PCI_FIXUP_FINAL. Standard ASPM L1 still > > applies, so the link still benefits from the deepest substate the > > BMG silicon handles correctly. The quirk keys on the card upstream > > port, which is shared across the BMG product family, so it covers > > all current BMG SKUs without enumerating individual GPU-endpoint > > IDs. > > > > The patch is in the attached intel-bmg-disable-l1ss.patch. With the > > patch applied, pcie_aspm.policy=powersupersave boots cleanly on this > > hardware (verification in progress at time of report). > > > > Empirical narrowing -- ASPM_L1.1 specifically is the trigger. > > > > An intermediate version of the quirk passed only > > PCIE_LINK_STATE_L1_1 | PCIE_LINK_STATE_L1_2 to > > pci_disable_link_state(), leaving the PCI-PM substate bits armed. > > After applying that variant, lspci reported > > > > L1SubCtl1: PCI-PM_L1.2- PCI-PM_L1.1+ ASPM_L1.2- ASPM_L1.1- > > > > on the BMG upstream port -- i.e. only the two ASPM substate bits > > were cleared, the PCI-PM substate bits stayed armed -- yet the > > system booted, xe bound, and the GPU operated normally. Combined > > with the AMD root port advertising only ASPM_L1.1+ (not L1.2), > > this isolates ASPM_L1.1 as the specific bit whose activation > > bricks the BMG card. The PCI-PM L1.x substates were also disabled > > in the final patch for hygiene, but they are not load-bearing for > > the fix on this hardware (the GPU does not enter D3hot during > > normal operation, so PCI-PM substates are inert). > > > > Remaining open questions for review: > > > > 1. Is the underlying defect in the AMD Starship root port (cannot > > wake the link from ASPM_L1.1) or in the BMG e2ff upstream port > > (cannot exit ASPM_L1.1 cleanly)? If the former, future BMG > > cards on Intel platforms may not need this quirk; if the > > latter, the quirk is correct for BMG everywhere. We do not > > have a non-AMD reproducer to disambiguate. > > > > 2. Should the quirk also apply to the AMD Starship/Matisse GPP > > Bridge itself (1022:1483 / 1022:1484-class IDs, see > > lspci-nn.txt)? That would be a broader brushstroke but might > > protect other devices presenting the same negotiation. > > > > > > ================================================================ > > WORKAROUND IN USE > > ================================================================ > > > > Until the quirk lands upstream, downstream users on this hardware > > must boot with pcie_aspm.policy=powersave (or default), losing > > ~25 W of idle savings that the deeper substates would otherwise > > provide. > > > > > > ================================================================ > > ATTACHMENTS > > ================================================================ > > > > Tarballs produced by debug/20260507-aspm-capture.sh: > > > > 20260507-204348-powersave-7.0.3.tar.zst > > -- working baseline > > > > 20260507-205055-powersupersave-7.0.3.tar.zst > > -- failed reproduction > > > > Each tarball contains: > > > > manifest.txt kernel, policy, hostname, GPU BDFs > > cmdline.txt kernel command line > > uname.txt kernel version > > nixos.txt userspace metadata > > dmidecode.txt BIOS/board info > > lspci-tree.txt PCI topology > > lspci-nn.txt PCI device list > > lspci-vvv-all.txt full system lspci -vvv > > > > gpu-03_00_0/ per-device captures for the GPU and > > every PCI ancestor up to the root > > complex: > > lspci-vvv.txt GPU > > parent-0-02_01_0.txt BMG card-internal downstream switch > > parent-1-01_00_0.txt BMG card upstream port (e2ff) > > parent-2-00_01_1.txt AMD root port > > sysfs.txt selected sysfs attributes > > > > dmesg-full.txt full kernel ring buffer > > dmesg-relevant.txt filtered for PCI/xe/ASPM/L1 > > journal-kernel-current-boot.txt > > journal-kernel-prev-boot.txt > > drivers.txt xe / i915 driver state, > > /sys/class/drm > > > > Patch: intel-bmg-disable-l1ss.patch (attached separately) > > > > NixOS 26.05 (nixpkgsRevision: > > 549bd84d6279f9852cae6225e372cc67fb91a4c1) > > > > Kernel: > > 7.0.3 #1-NixOS SMP PREEMPT_DYNAMIC Thu Apr 30 09:13:05 UTC 2026 > > > > > PCI/ASPM: disable L1.1/L1.2 substates for Intel Battlemage discrete GPU upstream port > > > > Intel Battlemage (BMG-G21 / BMG-G31, e.g. Arc Pro B70) discrete GPU cards > > expose a two-layer on-card PCIe switch: > > > > AMD/Intel root port <-> 8086:e2ff (BMG card upstream) > > 8086:e2f0 (BMG card downstream) > > 8086:e22x (BMG GPU endpoint, e.g. e223 = Arc Pro B70) > > > > The platform-facing link (root port <-> 8086:e2ff) is the only link in the > > chain that advertises L1 PM Substates support on both ends. On AMD > > Starship/Matisse (Ryzen 5xxx) root ports, the intersection is ASPM_L1.1 > > only (the AMD port advertises L1.1 but not L1.2). When pcie_aspm.policy= > > powersupersave arms ASPM_L1.1 on this link, the BMG card cannot recover > > from the resulting low-power state on subsequent D3cold->D0 transition, > > leaving the device permanently inaccessible: > > > > pcieport 0000:02:01.0: Unable to change power state from D3cold to D0, device inaccessible > > xe 0000:03:00.0: Unable to change power state from D3cold to D0, device inaccessible > > xe 0000:03:00.0: [drm] Running in SR-IOV VF mode [misdetected: dead config space] > > xe 0000:03:00.0: [drm] *ERROR* VF: Tile0: GT0: Failed to reset GuC state (-EPROTO) > > xe 0000:03:00.0: probe with driver xe failed with error -71 > > > > Reproduces deterministically on Linux 7.0.3 with an Arc Pro B70 in an > > AMD Ryzen 9 5950X system. pcie_aspm.policy=powersave (L0s+L1 only, no > > substates) works correctly; pcie_aspm.policy=powersupersave bricks the > > card on every boot. The 6.x-era blanket `no_d3cold` quirk for Battlemage > > was narrowed to ASUS NUC13 only in 7.0, but that change is orthogonal: > > the failure here is link-state, not device-state, and surfaces > > regardless of d3cold_allowed. > > > > Disable all four L1SS substates (ASPM_L1.1, ASPM_L1.2, PCI-PM_L1.1, > > PCI-PM_L1.2) on the BMG card's upstream port via a final PCI fixup. > > Standard ASPM L1 still applies, so the link still benefits from the > > deepest substate the BMG silicon actually handles correctly. The > > quirk is keyed on the upstream-port device ID 0xe2ff so it covers > > all current Battlemage SKUs (the GPU-endpoint ID varies by SKU, but > > the upstream switch is shared). > > > > Empirical narrowing (verified post-fix): with a partial mask that > > disabled only ASPM_L1.{1,2} but left PCI-PM_L1.{1,2} armed, the > > system boots and operates correctly. This isolates ASPM_L1.1 as the > > specific trigger of the brick (the AMD root port advertises ASPM_L1.1 > > but not ASPM_L1.2, so ASPM_L1.2 cannot have been activated). The > > PCI-PM substates only activate during D3hot transitions which the > > GPU does not undergo during normal use; they are disabled here for > > hygiene rather than necessity. > > > > Reported-by: Pavel Shirshov > > Signed-off-by: > > > > --- a/drivers/pci/quirks.c > > +++ b/drivers/pci/quirks.c > > @@ -6289,6 +6289,34 @@ DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x56b0, aspm_l1_acceptable_latency > > DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x56b1, aspm_l1_acceptable_latency); > > DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x56c0, aspm_l1_acceptable_latency); > > DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x56c1, aspm_l1_acceptable_latency); > > + > > +/* > > + * Intel Battlemage discrete GPU cards (BMG-G21 / BMG-G31; Arc B580, > > + * Arc Pro B50/B60/B70) expose a two-layer on-card PCIe switch. The > > + * platform-facing link, between the host root port and the card's > > + * upstream switch port (PCI device ID 0xe2ff), is the only link in the > > + * chain advertising L1 PM Substates on both ends. On at least AMD > > + * Starship/Matisse root ports, where the intersection is ASPM_L1.1 > > + * only, arming L1.1 leaves the BMG card unable to wake from D3cold: > > + * > > + * pcieport 0000:02:01.0: Unable to change power state from D3cold > > + * to D0, device inaccessible > > + * xe 0000:03:00.0: probe with driver xe failed with error -71 > > + * > > + * Reproduces deterministically with pcie_aspm.policy=powersupersave, > > + * works correctly with policy=powersave (no substates). Disable L1SS > > + * substates on the BMG card upstream port; standard L1 ASPM is > > + * unaffected. > > + */ > > +static void quirk_intel_bmg_no_l1ss(struct pci_dev *dev) > > +{ > > + pci_disable_link_state(dev, PCIE_LINK_STATE_L1_2 | > > + PCIE_LINK_STATE_L1_1 | > > + PCIE_LINK_STATE_L1_2_PCIPM | > > + PCIE_LINK_STATE_L1_1_PCIPM); > > + pci_info(dev, "intel-bmg-aspm-quirk: L1.1/L1.2 substates disabled on BMG upstream port\n"); > > +} > > +DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0xe2ff, quirk_intel_bmg_no_l1ss); > > #endif > > > > #ifdef CONFIG_PCIE_DPC > > --45621f1d45c0b2532bd65f862dc8ff0c0dae435b Content-Type: text/html Content-Transfer-Encoding: quoted-printable
Yes, still a= problem, powersupersave kills BM cards, at least on my machines.
<= div>

On Fri, Sep 18, 2026, at 21:33, Bjorn = Helgaas wrote:
= On Thu, May 07, 2026 at 11:14:04PM +0100, Pavel Shirshov wrote:
> The report and the patch below are completely claude'd but the qu= irk in the patch works.
> 
> PCI/ASPM: In= tel Battlemage (Arc Pro B70) bricks at boot when
> pcie_asp= m.policy=3Dpowersupersave enables ASPM_L1.1 on AMD root port link
<= div>
I happened on this report that we never responded to.=   I assume this
is still a problem?

<= div>It looks like it's not a regression, but should still be fixed.

> =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
> SUMMARY
> =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D
> 
> On Linux 7.0.3, an I= ntel Arc Pro B70 (Battlemage / BMG-G31, GPU PCI
> ID 8086:e= 223) plugged into an AMD Ryzen 9 5950X system fails to wake
&g= t; from D3cold during PCI core enumeration when the kernel is booted
> with pcie_aspm.policy=3Dpowersupersave. The card is permanen= tly
> inaccessible until reboot with a different policy.
> pcie_aspm.policy=3Dpowersave (L0s+L1, no substates) works c= orrectly.
> 
> The failure surfaces in PC= I core first; downstream xe driver bind
> then fails with -= EPROTO:
> 
>     pcie= port 0000:02:01.0: Unable to change power state from D3cold
&g= t;           &nbs= p;           &nbs= p;    to D0, device inaccessible
> &nbs= p;   pcieport 0000:02:02.0: Unable to change power state from = D3cold
>        &nb= sp;           &nb= sp;       to D0, device inaccessible
=
>     xe 0000:03:00.0: Unable to change powe= r state from D3cold to D0,
>     &= nbsp;           &= nbsp;    device inaccessible
>  &n= bsp;  xe 0000:03:00.0: [drm] Running in SR-IOV VF mode
&g= t;           &nbs= p;          [misdetected: d= ead config space reads as 0xff]
>     x= e 0000:03:00.0: [drm] *ERROR* VF: Tile0: GT0: Failed to reset
= >           &n= bsp;          GuC state (-E= PROTO)
>     xe 0000:03:00.0: probe wit= h driver xe failed with error -71
> 
> Af= ter the brick, "lspci -vvv -s 03:00.0" reports
> "!!! Unkno= wn header type 7f" -- the canonical signature of a PCI
> de= vice whose config space reads return all-ones, i.e. the link to the
> device is dead.
> 
> 
> =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
&= gt; HARDWARE
> =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D
> 
> CPU / root complex:
&g= t;     AMD Ryzen 9 5950X (Starship/Matisse). The roo= t port hosting the
>     BMG card is 00= 00:00:01.1 -- "Advanced Micro Devices, Inc. [AMD]
> &n= bsp;   Starship/Matisse GPP Bridge" (subsystem 1022:1453).
> 
> GPU:
>   &n= bsp; Intel Arc Pro B70 -- 8086:e223 (BMG-G31, subsystem 8086:1701).
> 
> On-card topology -- the card has a two-l= ayer on-board PCIe switch:
>     0000:0= 1:00.0  Intel 8086:e2ff -- BMG card upstream switch port,
>           &= nbsp;           &= nbsp;           &= nbsp;  PCIe 5.0 x16 capable (currently
>  &n= bsp;           &n= bsp;           &n= bsp;           downgra= ded to Gen4 x16).
>     0000:02:01.0&nb= sp; Intel 8086:e2f0 -- BMG card downstream switch
> &n= bsp;           &n= bsp;           &n= bsp;            p= ort, PCIe Gen1 x1 internal.
>     0000:= 03:00.0  Intel 8086:e223 -- GPU endpoint, PCIe Gen1 x1
&g= t;           &nbs= p;           &nbs= p;           &nbs= p;  internal.
> 
> Other:
= >     BIOS has PCIe ASPM enabled in firmware. pci= e_aspm=3Dforce is NOT
>     set on the = kernel command line. Motherboard: ASRock X570
>  =    (specifics in attached dmidecode.txt).
> =
> 
> =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D
> REPRODUCER
> =3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
> 
> Boot = any kernel >=3D 7.0 with kernel command line containing:
&g= t; 
>     pcie_aspm.policy=3Dpower= supersave xe.force_probe=3D*
> 
> (Also r= eproduces under earlier 6.x kernels.)
> 
>= ; Reverting the cmdline to "pcie_aspm.policy=3Dpowersave" and rebooting<= /div>
> restores the card. No firmware reset is required between = attempts --
> the brick is purely a runtime link-state fail= ure during kernel boot.
> 
> 
<= div>> =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
>= ASPM NEGOTIATION
> =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D
> 
> Captured with "lspci -vvv"= on a working policy=3Dpowersave boot
> (attached: 20260507= -204348-powersave-7.0.3.tar.zst).
> 
> Li= nk 1: 00:01.1 AMD root  <->  01:00.0 BMG upstream
<= div>>     Lower end (AMD root, L1SubCap):
>         PCI-PM_L1.2-&nbs= p; PCI-PM_L1.1+  ASPM_L1.2-  ASPM_L1.1+
> &n= bsp;   Upper end (BMG upstream, L1SubCap):
> = ;        PCI-PM_L1.2+  PCI-PM_L1= .1+  ASPM_L1.2+  ASPM_L1.1+
>   &n= bsp; Active L1SubCtl1 under policy=3Dpowersave:
> &nbs= p;       PCI-PM_L1.2-  PCI-PM_L1.1-&n= bsp; ASPM_L1.2-  ASPM_L1.1-
> 
> Lin= k 2: 01:00.0  <->  02:01.0   (card-internal sw= itch)
>     No L1SS capability advertis= ed on either end.
> 
> Link 3: 02:01.0&nb= sp; <->  03:00.0   (card-internal to GPU)
>     No L1SS capability advertised on either en= d.
> 
> Conclusion: only Link 1 -- the pl= atform-facing AMD<->BMG link -- is
> L1SS-capable on = both ends, and the intersection is ASPM_L1.1 only
> (the AM= D GPP root port advertises L1.1 but not L1.2). With
> polic= y=3Dpowersupersave, the kernel arms ASPM_L1.1 on this link. After
<= div>> that, every D3cold->D0 transition fails.
> = ;
> Both ends advertise multi-retimer support (Retimer+ 2Re= timers+ on
> the AMD root port and on the BMG upstream port= ). Retimers + L1SS
> have a history of wake-recovery proble= ms on other platforms; this
> may be the same class of issu= e.
> 
> 
> =3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
> TIMELINE -- failed b= oot, kernel 7.0.3
> =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D
> 
> Excerpted from dmesg-relev= ant.txt in the powersupersave capture:
> 
&g= t;     28.792s  pcieport 0000:00:01.1: PME: Sig= naling with IRQ 48
>      &nb= sp;           &nb= sp;   [AMD root port for BMG]
>   =   28.842s  pcieport 0000:02:01.0: Unable to change power state= from
>        &nbs= p;           &nbs= p; D3cold to D0, device inaccessible
>   &nb= sp; 28.843s  pcieport 0000:02:02.0: Unable to change power state fr= om
>         &= nbsp;            = D3cold to D0, device inaccessible
>    = ...
>     29.034s  xe 0000:03:00.= 0: Unable to change power state from
>   &nb= sp;           &nb= sp;      D3cold to D0, device inaccessible
>     29.035s  xe 0000:03:00.0: [drm] = Running in SR-IOV VF mode
>     29.035s=   xe 0000:03:00.0: [drm] *ERROR* VF: Tile0: GT0: Failed
&= gt;           &nb= sp;          to reset GuC s= tate (-EPROTO)
>     29.035s  xe 0= 000:03:00.0: probe with driver xe failed with
>  =             =         error -71
> = ;
> The PCI core's first wake attempt at 28.842s (the immed= iate parent
> bridge of the BMG GPU) fails before any drive= r probe runs. This
> confirms the failure is in the PCI/ASP= M layer, not in xe; xe just
> sees the resulting dead confi= g space and misclassifies the PF as a
> VF.
>&= nbsp;
> 
> =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D
> WORKING-POLICY LSPCI EXCERPTS  (r= elevant capabilities)
> =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D
> 
> policy=3Dpowersave base= line, root port 00:01.1:
> 
>  =    LnkCap:  Speed 16GT/s, Width x16, ASPM L1, Exit Latenc= y L1 <64us
>     LnkCtl:  ASPM = L1 Enabled
>     LnkSta:  Speed 16= GT/s, Width x16
>     Capabilities: [37= 0 v1] L1 PM Substates
>      =    L1SubCap:  PCI-PM_L1.2- PCI-PM_L1.1+ ASPM_L1.2- ASPM_L= 1.1+
>         = ;           L1_PM_Subs= tates+
>         L1= SubCtl1: PCI-PM_L1.2- PCI-PM_L1.1- ASPM_L1.2- ASPM_L1.1-
>&= nbsp;        L1SubCtl2:
>= ; 
> policy=3Dpowersave baseline, BMG upstream 01:00.0= :
> 
>     LnkCap:&nb= sp; Speed 32GT/s, Width x16, ASPM L1, Exit Latency L1 <32us
>     LnkCtl:  ASPM L1 Enabled
&g= t;     LnkSta:  Speed 16GT/s (downgraded), Widt= h x16
>     Capabilities: [244 v1] L1 P= M Substates
>       &nbs= p; L1SubCap:  PCI-PM_L1.2+ PCI-PM_L1.1+ ASPM_L1.2+ ASPM_L1.1+
=
>          &nb= sp;         L1_PM_Substates+
>         L1SubCtl1: P= CI-PM_L1.2- PCI-PM_L1.1- ASPM_L1.2- ASPM_L1.1-
>  = ;       L1SubCtl2: T_PwrOn=3D14us
> 
> 
> =3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D
> PROPOSED FIX
> =3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
> 
> Disable both L1SS substates on the BMG card's upstream switch por= t
> (8086:e2ff) via a DECLARE_PCI_FIXUP_FINAL. Standard ASP= M L1 still
> applies, so the link still benefits from the d= eepest substate the
> BMG silicon handles correctly. The qu= irk keys on the card upstream
> port, which is shared acros= s the BMG product family, so it covers
> all current BMG SK= Us without enumerating individual GPU-endpoint
> IDs.
=
> 
> The patch is in the attached intel-bmg-disable-l1ss.patch. With the
> 
>   An intermediate version of the quirk passed on= ly
>   PCIE_LINK_STATE_L1_1 | PCIE_LINK_STATE_L1_= 2 to
>   pci_disable_link_state(), leaving the PC= I-PM substate bits armed.
>   After applying that= variant, lspci reported
> 
>  =      L1SubCtl1: PCI-PM_L1.2- PCI-PM_L1.1+ ASPM_L1.2-= ASPM_L1.1-
> 
>   on the BMG u= pstream port -- i.e. only the two ASPM substate bits
> = ;  were cleared, the PCI-PM substate bits stayed armed -- yet the
>   system booted, xe bound, and the GPU operated = normally. Combined
>   with the AMD root port adv= ertising only ASPM_L1.1+ (not L1.2),
>   this iso= lates ASPM_L1.1 as the specific bit whose activation
> = ;  bricks the BMG card. The PCI-PM L1.x substates were also disable= d
>   in the final patch for hygiene, but they ar= e not load-bearing for
>   the fix on this hardwa= re (the GPU does not enter D3hot during
>   norma= l operation, so PCI-PM substates are inert).
> 
<= div>> Remaining open questions for review:
> 
=
>   1. Is the underlying defect in the AMD Starship ro= ot port (cannot
>      wake the li= nk from ASPM_L1.1) or in the BMG e2ff upstream port
> =      (cannot exit ASPM_L1.1 cleanly)? If the former,= future BMG
>      cards on Intel = platforms may not need this quirk; if the
>  &nbs= p;   latter, the quirk is correct for BMG everywhere. We do no= t
>      have a non-AMD reproducer= to disambiguate.
> 
>   2. Sho= uld the quirk also apply to the AMD Starship/Matisse GPP
>&= nbsp;     Bridge itself (1022:1483 / 1022:1484-class= IDs, see
>      lspci-nn.txt)? Th= at would be a broader brushstroke but might
>  &n= bsp;   protect other devices presenting the same negotiation.<= /div>
> 
> 
> =3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
> WORKAROUND IN USE
=
> =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
>=  
> Until the quirk lands upstream, downstream users o= n this hardware
> must boot with pcie_aspm.policy=3Dpowersa= ve (or default), losing
> ~25 W of idle savings that the de= eper substates would otherwise
> provide.
>&nb= sp;
> 
> =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D
> ATTACHMENTS
> =3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
> 
> Ta= rballs produced by debug/20260507-aspm-capture.sh:
> <= /div>
>     20260507-204348-powersave-7.0.3.t= ar.zst
>         --= working baseline
> 
>   &= nbsp; 20260507-205055-powersupersave-7.0.3.tar.zst
> &= nbsp;       -- failed reproduction
> 
> Each tarball contains:
> =
>     manifest.txt   &n= bsp;       kernel, policy, hostname, GPU B= DFs
>     cmdline.txt   =          kernel command line
>     uname.txt    &nb= sp;         kernel version
=
>     nixos.txt     = ;         userspace metadata
>     dmidecode.txt    = ;      BIOS/board info
> &nbs= p;   lspci-tree.txt       &= nbsp; PCI topology
>     lspci-nn.txt&n= bsp;          PCI device li= st
>     lspci-vvv-all.txt  &= nbsp;   full system lspci -vvv
> 
= >     gpu-03_00_0/     &= nbsp;     per-device captures for the GPU and
<= div>>          &nbs= p;           &nbs= p;     every PCI ancestor up to the root
&= gt;           &nb= sp;           &nb= sp;    complex:
>    &nb= sp;    lspci-vvv.txt      &= nbsp;   GPU
>      =    parent-0-02_01_0.txt   BMG card-internal downstre= am switch
>        = parent-1-01_00_0.txt   BMG card upstream port (e2ff)
>         parent-2-00_01_1.= txt   AMD root port
>    &nbs= p;    sysfs.txt       =        selected sysfs attributes
> 
>     dmesg-full.txt &= nbsp;           &= nbsp;  full kernel ring buffer
>   &nbs= p; dmesg-relevant.txt        &nb= sp;   filtered for PCI/xe/ASPM/L1
>  &n= bsp;  journal-kernel-current-boot.txt
>  &nb= sp;  journal-kernel-prev-boot.txt
>   &= nbsp; drivers.txt         &= nbsp;         xe / i915 driver s= tate,
>        &nbs= p;           &nbs= p;           &nbs= p;  /sys/class/drm
> 
> 
>= NixOS 26.05 (nixpkgsRevision:
>     54= 9bd84d6279f9852cae6225e372cc67fb91a4c1)
> 
&= gt; Kernel:
>     7.0.3 #1-NixOS SMP PR= EEMPT_DYNAMIC Thu Apr 30 09:13:05 UTC 2026


=

> PCI/ASPM: disable L1.1/L1.2 substates for= Intel Battlemage discrete GPU upstream port
> 
<= div>> Intel Battlemage (BMG-G21 / BMG-G31, e.g. Arc Pro B70) discrete= GPU cards
> expose a two-layer on-card PCIe switch:
<= div>> 
>     AMD/Intel root por= t  <->  8086:e2ff (BMG card upstream)
>&nbs= p;           &nbs= p;           &nbs= p;      8086:e2f0 (BMG card downstream)
>           = ;            = ;        8086:e22x (BMG GPU endpoint,= e.g. e223 =3D Arc Pro B70)
> 
> The plat= form-facing link (root port <-> 8086:e2ff) is the only link in the=
> chain that advertises L1 PM Substates support on both en= ds. On AMD
> Starship/Matisse (Ryzen 5xxx) root ports, the = intersection is ASPM_L1.1
> only (the AMD port advertises L= 1.1 but not L1.2). When pcie_aspm.policy=3D
> powersupersav= e arms ASPM_L1.1 on this link, the BMG card cannot recover
>= ; from the resulting low-power state on subsequent D3cold->D0 transit= ion,
> leaving the device permanently inaccessible:
> 
>     pcieport 0000:02:01= .0: Unable to change power state from D3cold to D0, device inaccessible<= /div>
>     xe 0000:03:00.0: Unable to change= power state from D3cold to D0, device inaccessible
> =     xe 0000:03:00.0: [drm] Running in SR-IOV VF mode = ;   [misdetected: dead config space]
>  = ;   xe 0000:03:00.0: [drm] *ERROR* VF: Tile0: GT0: Failed to r= eset GuC state (-EPROTO)
>     xe 0000:= 03:00.0: probe with driver xe failed with error -71
> =
> Reproduces deterministically on Linux 7.0.3 with an Arc = Pro B70 in an
> AMD Ryzen 9 5950X system. pcie_aspm.policy=3D= powersave (L0s+L1 only, no
> substates) works correctly; pc= ie_aspm.policy=3Dpowersupersave bricks the
> card on every = boot. The 6.x-era blanket `no_d3cold` quirk for Battlemage
>= ; was narrowed to ASUS NUC13 only in 7.0, but that change is orthogonal:=
> the failure here is link-state, not device-state, and su= rfaces
> regardless of d3cold_allowed.
> =
> Disable all four L1SS substates (ASPM_L1.1, ASPM_L1.2, P= CI-PM_L1.1,
> PCI-PM_L1.2) on the BMG card's upstream port = via a final PCI fixup.
> Standard ASPM L1 still applies, so= the link still benefits from the
> deepest substate the BM= G silicon actually handles correctly. The
> quirk is keyed = on the upstream-port device ID 0xe2ff so it covers
> all cu= rrent Battlemage SKUs (the GPU-endpoint ID varies by SKU, but
= > the upstream switch is shared).
> 
>= Empirical narrowing (verified post-fix): with a partial mask that
=
> disabled only ASPM_L1.{1,2} but left PCI-PM_L1.{1,2} armed, th= e
> system boots and operates correctly. This isolates ASPM= _L1.1 as the
> specific trigger of the brick (the AMD root = port advertises ASPM_L1.1
> but not ASPM_L1.2, so ASPM_L1.2= cannot have been activated). The
> PCI-PM substates only a= ctivate during D3hot transitions which the
> GPU does not u= ndergo during normal use; they are disabled here for
> hygi= ene rather than necessity.
> 
> Reported-= by: Pavel Shirshov <pavel@7mind.io<= /a>>
> --- a/drivers/pci/quirks.c<= /div>
> +++ b/drivers/pci/quirks.c
> @@ -6289,6 +628= 9,34 @@ DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x56b0, aspm_l1_ac= ceptable_latency
>  DECLARE_PCI_FIXUP_HEADER(PCI_VENDO= R_ID_INTEL, 0x56b1, aspm_l1_acceptable_latency);
>  DE= CLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x56c0, aspm_l1_acceptable_l= atency);
>  DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INT= EL, 0x56c1, aspm_l1_acceptable_latency);
> +
>= +/*
> + * Intel Battlemage discrete GPU cards (BMG-G21 / B= MG-G31; Arc B580,
> + * Arc Pro B50/B60/B70) expose a two-l= ayer on-card PCIe switch. The
> + * platform-facing link, b= etween the host root port and the card's
> + * upstream swi= tch port (PCI device ID 0xe2ff), is the only link in the
> = + * chain advertising L1 PM Substates on both ends. On at least AMD
> + * Starship/Matisse root ports, where the intersection is AS= PM_L1.1
> + * only, arming L1.1 leaves the BMG card unable = to wake from D3cold:
> + *
> + *   p= cieport 0000:02:01.0: Unable to change power state from D3cold
> + *          &nb= sp;           &nb= sp;   to D0, device inaccessible
> + *  = ; xe 0000:03:00.0: probe with driver xe failed with error -71
= > + *
> + * Reproduces deterministically with pcie_aspm.= policy=3Dpowersupersave,
> + * works correctly with policy=3D= powersave (no substates). Disable L1SS
> + * substates on t= he BMG card upstream port; standard L1 ASPM is
> + * unaffe= cted.
> + */
> +static void quirk_intel_bmg_no= _l1ss(struct pci_dev *dev)
> +{
> + pci_disabl= e_link_state(dev, PCIE_LINK_STATE_L1_2 |
> +   = ;  PCIE_LINK_STATE_L1_1 |
> +     PC= IE_LINK_STATE_L1_2_PCIPM |
> +     PCIE_L= INK_STATE_L1_1_PCIPM);
> + pci_info(dev, "intel-bmg-aspm-qu= irk: L1.1/L1.2 substates disabled on BMG upstream port\n");
&g= t; +}
> +DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0xe2f= f, quirk_intel_bmg_no_l1ss);
>  #endif
>&= nbsp;
>  #ifdef CONFIG_PCIE_DPC


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