Re: [PATCH v2] drm/xe/xe_gt_idle: fix vecs config for powergating info

["Nilawar, Badal" <badal.nilawar@intel.com>]

On 18-08-2026 10:30, Ashutosh Dixit wrote:
> vecs configuration for newer platforms (media version >= 35) is
> different. Fix powergating info for these platforms.
>
> Bspec: 67103, 77977
>
> Signed-off-by: Ashutosh Dixit <ashutosh.dixit@intel.com>
> ---
> v2: Restrict to two media slices (Badal Nilawar)
> ---
>   drivers/gpu/drm/xe/xe_gt_idle.c | 45 +++++++++++++++++++++++----------
>   1 file changed, 32 insertions(+), 13 deletions(-)
>
> diff --git a/drivers/gpu/drm/xe/xe_gt_idle.c b/drivers/gpu/drm/xe/xe_gt_idle.c
> index 04b24e1c8b78e..98bd4d87ba184 100644
> --- a/drivers/gpu/drm/xe/xe_gt_idle.c
> +++ b/drivers/gpu/drm/xe/xe_gt_idle.c
> @@ -208,26 +208,34 @@ int xe_gt_idle_pg_print(struct xe_gt *gt, struct drm_printer *p)
>   	/*
>   	 * Media Slices
>   	 *
> -	 * Slice 0: VCS0, VCS1, VECS0
> -	 * Slice 1: VCS2, VCS3, VECS1
> -	 * Slice 2: VCS4, VCS5, VECS2
> -	 * Slice 3: VCS6, VCS7, VECS3
> +	 * Prior to MEDIA_VER 35		Post MEDIA_VER 35
> +	 *
> +	 * Slice 0: VCS0, VCS1, VECS0, VECS2	Slice 0: VCS0, VCS1, VECS0, VECS1
> +	 * Slice 1: VCS2, VCS3, VECS1, VECS3	Slice 1: VCS2, VCS3, VECS2, VECS3
>   	 */
> -	static const struct {
> +	struct media_slice {
>   		u64 engines;
>   		u32 status_bit;
> -	} media_slices[] = {
> +	};
> +
> +	static const struct media_slice media_slices_pre_35[] = {
>   		{(BIT(XE_HW_ENGINE_VCS0) | BIT(XE_HW_ENGINE_VCS1) |
> -		  BIT(XE_HW_ENGINE_VECS0)), MEDIA_SLICE0_AWAKE_STATUS},
> +		  BIT(XE_HW_ENGINE_VECS0) | BIT(XE_HW_ENGINE_VECS2)),
> +		 MEDIA_SLICE0_AWAKE_STATUS},
>   
>   		{(BIT(XE_HW_ENGINE_VCS2) | BIT(XE_HW_ENGINE_VCS3) |
> -		   BIT(XE_HW_ENGINE_VECS1)), MEDIA_SLICE1_AWAKE_STATUS},
> +		   BIT(XE_HW_ENGINE_VECS1) | BIT(XE_HW_ENGINE_VECS3)),
> +		 MEDIA_SLICE1_AWAKE_STATUS},
> +	};
>   
> -		{(BIT(XE_HW_ENGINE_VCS4) | BIT(XE_HW_ENGINE_VCS5) |
> -		   BIT(XE_HW_ENGINE_VECS2)), MEDIA_SLICE2_AWAKE_STATUS},
> +	static const struct media_slice media_slices_post_35[] = {
> +		{(BIT(XE_HW_ENGINE_VCS0) | BIT(XE_HW_ENGINE_VCS1) |
> +		  BIT(XE_HW_ENGINE_VECS0) | BIT(XE_HW_ENGINE_VECS1)),
> +		 MEDIA_SLICE0_AWAKE_STATUS},
>   
> -		{(BIT(XE_HW_ENGINE_VCS6) | BIT(XE_HW_ENGINE_VCS7) |
> -		   BIT(XE_HW_ENGINE_VECS3)), MEDIA_SLICE3_AWAKE_STATUS},
> +		{(BIT(XE_HW_ENGINE_VCS2) | BIT(XE_HW_ENGINE_VCS3) |
> +		   BIT(XE_HW_ENGINE_VECS2) | BIT(XE_HW_ENGINE_VECS3)),
> +		 MEDIA_SLICE1_AWAKE_STATUS},
>   	};

Looks good to me.

Reviewed-by: Badal Nilawar <badal.nilawar@intel.com>

Thanks,
Badal

>   
>   	if (xe->info.platform == XE_PVC) {
> @@ -261,10 +269,21 @@ int xe_gt_idle_pg_print(struct xe_gt *gt, struct drm_printer *p)
>   
>   	/* Print media CPG status only if media is present */
>   	if (vcs_mask || vecs_mask) {
> +		const struct media_slice *media_slices;
> +		int num_media_slices;
> +
> +		if (MEDIA_VERx100(gt_to_xe(gt)) < 3500) {
> +			media_slices = media_slices_pre_35;
> +			num_media_slices = ARRAY_SIZE(media_slices_pre_35);
> +		} else {
> +			media_slices = media_slices_post_35;
> +			num_media_slices = ARRAY_SIZE(media_slices_post_35);
> +		}
> +
>   		drm_printf(p, "Media Power Gating Enabled: %s\n",
>   			   str_yes_no(pg_enabled & MEDIA_POWERGATE_ENABLE));
>   
> -		for (n = 0; n < ARRAY_SIZE(media_slices); n++)
> +		for (n = 0; n < num_media_slices; n++)
>   			if (gt->info.engine_mask & media_slices[n].engines)
>   				drm_printf(p, "Media Slice%d Power Gate Status: %s\n", n,
>   					   str_up_down(pg_status & media_slices[n].status_bit));