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mx.microsoft.com 1; spf=pass smtp.mailfrom=intel.com; dmarc=pass action=none header.from=intel.com; dkim=pass header.d=intel.com; arc=none Authentication-Results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=intel.com; Received: from IA0PR11MB7307.namprd11.prod.outlook.com (2603:10b6:208:437::10) by MN0PR11MB6184.namprd11.prod.outlook.com (2603:10b6:208:3c4::11) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.9253.13; Fri, 24 Oct 2025 07:14:21 +0000 Received: from IA0PR11MB7307.namprd11.prod.outlook.com ([fe80::dafa:d38d:8ac1:e843]) by IA0PR11MB7307.namprd11.prod.outlook.com ([fe80::dafa:d38d:8ac1:e843%6]) with mapi id 15.20.9253.011; Fri, 24 Oct 2025 07:14:21 +0000 Message-ID: <35cc96f3-6e8f-458e-9ebf-8789a5e9312a@intel.com> Date: Fri, 24 Oct 2025 12:44:15 +0530 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 21/25] drm/i915/ltphy: Define function to readout LT Phy PLL state To: Suraj Kandpal , , CC: , , , References: <20251015040817.3431297-1-suraj.kandpal@intel.com> <20251015040817.3431297-22-suraj.kandpal@intel.com> Content-Language: en-US From: "Murthy, Arun R" In-Reply-To: <20251015040817.3431297-22-suraj.kandpal@intel.com> Content-Type: text/plain; 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> } > > +static void xe3plpd_ddi_get_config(struct intel_encoder *encoder, > + struct intel_crtc_state *crtc_state) > +{ > + intel_lt_phy_pll_readout_hw_state(encoder, crtc_state, &crtc_state->dpll_hw_state.ltpll); > + > + if (crtc_state->dpll_hw_state.ltpll.tbt_mode) > + crtc_state->port_clock = intel_mtl_tbt_calc_port_clock(encoder); > + else > + crtc_state->port_clock = > + intel_lt_phy_calc_port_clock(encoder, crtc_state); > + intel_ddi_get_config(encoder, crtc_state); > +} > + > static void mtl_ddi_get_config(struct intel_encoder *encoder, > struct intel_crtc_state *crtc_state) > { > @@ -5234,6 +5247,7 @@ void intel_ddi_init(struct intel_display *display, > encoder->enable_clock = intel_xe3plpd_pll_enable; > encoder->disable_clock = intel_xe3plpd_pll_disable; > encoder->port_pll_type = intel_mtl_port_pll_type; > + encoder->get_config = xe3plpd_ddi_get_config; > } else if (DISPLAY_VER(display) >= 14) { > encoder->enable_clock = intel_mtl_pll_enable; > encoder->disable_clock = intel_mtl_pll_disable; > diff --git a/drivers/gpu/drm/i915/display/intel_lt_phy.c b/drivers/gpu/drm/i915/display/intel_lt_phy.c > index 0be4aad0efcc..11178cd00a5b 100644 > --- a/drivers/gpu/drm/i915/display/intel_lt_phy.c > +++ b/drivers/gpu/drm/i915/display/intel_lt_phy.c > @@ -1873,6 +1873,39 @@ intel_lt_phy_pll_compare_hw_state(const struct intel_lt_phy_pll_state *a, > return true; > } > > +void intel_lt_phy_pll_readout_hw_state(struct intel_encoder *encoder, > + const struct intel_crtc_state *crtc_state, > + struct intel_lt_phy_pll_state *pll_state) > +{ > + u8 owned_lane_mask; > + u8 lane; > + intel_wakeref_t wakeref; > + int i, j, k; > + > + pll_state->tbt_mode = intel_tc_port_in_tbt_alt_mode(enc_to_dig_port(encoder)); > + if (pll_state->tbt_mode) > + return; > + > + owned_lane_mask = intel_lt_phy_get_owned_lane_mask(encoder); > + lane = owned_lane_mask & INTEL_LT_PHY_LANE0 ? : INTEL_LT_PHY_LANE1; > + wakeref = intel_lt_phy_transaction_begin(encoder); > + > + pll_state->config[0] = intel_lt_phy_read(encoder, lane, LT_PHY_VDR_0_CONFIG); > + pll_state->config[1] = intel_lt_phy_read(encoder, INTEL_LT_PHY_LANE0, LT_PHY_VDR_1_CONFIG); > + pll_state->config[2] = intel_lt_phy_read(encoder, lane, LT_PHY_VDR_2_CONFIG); > + > + for (i = 0; i <= 12; i++) { > + for (j = 3, k = 0; j >= 0; j--, k++) > + pll_state->data[i][k] = > + intel_lt_phy_read(encoder, INTEL_LT_PHY_LANE0, > + LT_PHY_VDR_X_DATAY(i, j)); > + } > + > + pll_state->clock = > + intel_lt_phy_calc_port_clock(encoder, crtc_state); > + intel_lt_phy_transaction_end(encoder, wakeref); > +} > + > void intel_xe3plpd_pll_enable(struct intel_encoder *encoder, > const struct intel_crtc_state *crtc_state) > { > diff --git a/drivers/gpu/drm/i915/display/intel_lt_phy.h b/drivers/gpu/drm/i915/display/intel_lt_phy.h > index e93e5becc316..dd8cbb151b23 100644 > --- a/drivers/gpu/drm/i915/display/intel_lt_phy.h > +++ b/drivers/gpu/drm/i915/display/intel_lt_phy.h > @@ -28,6 +28,9 @@ void intel_lt_phy_dump_hw_state(struct intel_display *display, > bool > intel_lt_phy_pll_compare_hw_state(const struct intel_lt_phy_pll_state *a, > const struct intel_lt_phy_pll_state *b); > +void intel_lt_phy_pll_readout_hw_state(struct intel_encoder *encoder, > + const struct intel_crtc_state *crtc_state, > + struct intel_lt_phy_pll_state *pll_state); > void intel_xe3plpd_pll_enable(struct intel_encoder *encoder, > const struct intel_crtc_state *crtc_state); > void intel_xe3plpd_pll_disable(struct intel_encoder *encoder);