From: "Coelho, Luciano" <luciano.coelho@intel.com>
To: "Roper, Matthew D" <matthew.d.roper@intel.com>,
"De Marchi, Lucas" <lucas.demarchi@intel.com>
Cc: "intel-gfx@lists.freedesktop.org"
<intel-gfx@lists.freedesktop.org>,
"intel-xe@lists.freedesktop.org" <intel-xe@lists.freedesktop.org>
Subject: Re: [Intel-xe] [Intel-gfx] [PATCH 27/42] drm/i915/xe2lpd: Read pin assignment from IOM
Date: Thu, 24 Aug 2023 11:31:45 +0000 [thread overview]
Message-ID: <360724976ac1d6b8060a666fa51827fcbe2d500e.camel@intel.com> (raw)
In-Reply-To: <20230823202833.GI1529860@mdroper-desk1.amr.corp.intel.com>
On Wed, 2023-08-23 at 13:28 -0700, Matt Roper wrote:
> On Wed, Aug 23, 2023 at 10:07:25AM -0700, Lucas De Marchi wrote:
> > From: Luca Coelho <luciano.coelho@intel.com>
> >
> > Starting from display version 20, we need to read the pin assignment
> > from the IOM TCSS_DDI_STATUS register instead of reading it from the
> > FIA.
> >
> > We use the pin assignment to decide the maximum lane count. So, to
> > support this change, add a new lnl_tc_port_get_max_lane_count() function
> > that reads from the TCSS_DDI_STATUS register and decides the maximum
> > lane count based on that.
> >
> > BSpec: 69594
> > Cc: Mika Kahola <mika.kahola@intel.com>
> > Signed-off-by: Luca Coelho <luciano.coelho@intel.com>
> > Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
> > ---
> > drivers/gpu/drm/i915/display/intel_tc.c | 28 +++++++++++++++++++++++++
> > drivers/gpu/drm/i915/i915_reg.h | 1 +
> > 2 files changed, 29 insertions(+)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_tc.c b/drivers/gpu/drm/i915/display/intel_tc.c
> > index 3c94bbcb5497..37b0f8529b4f 100644
> > --- a/drivers/gpu/drm/i915/display/intel_tc.c
> > +++ b/drivers/gpu/drm/i915/display/intel_tc.c
> > @@ -290,6 +290,31 @@ u32 intel_tc_port_get_pin_assignment_mask(struct intel_digital_port *dig_port)
> > DP_PIN_ASSIGNMENT_SHIFT(tc->phy_fia_idx);
> > }
> >
> > +static int lnl_tc_port_get_max_lane_count(struct intel_digital_port *dig_port)
> > +{
> > + struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
> > + enum tc_port tc_port = intel_port_to_tc(i915, dig_port->base.port);
> > + intel_wakeref_t wakeref;
> > + u32 val, pin_assignment;
> > +
> > + with_intel_display_power(i915, POWER_DOMAIN_DISPLAY_CORE, wakeref)
>
> Do we need this? I don't think POWER_DOMAIN_DISPLAY_CORE has been tied
> to any power wells since VLV/CHV.
>
> Hmm, it looks like we actually grab it (and even assert it) in a bunch of
> places on modern platforms that don't make sense to me since it isn't
> tied to anything.
>
> I guess leaving this here doesn't hurt anything, although we might want
> to go back and take another look at this in the future.
>
> Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
Thanks, Matt! You have a good point, but as you said, maybe this should
be revisited in all occurrences and changed in one go. I just kept it
consistent with other usage.
--
Cheers,
Luca.
next prev parent reply other threads:[~2023-08-24 11:31 UTC|newest]
Thread overview: 106+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-08-23 17:06 [Intel-xe] [PATCH 00/42] Enable Lunar Lake display Lucas De Marchi
2023-08-23 17:06 ` [Intel-xe] [PATCH 01/42] drm/i915: Start using plane scale factor for relative data rate Lucas De Marchi
2023-08-23 17:07 ` [Intel-xe] [PATCH 02/42] drm/i915/display: Remove unused POWER_DOMAIN_MASK Lucas De Marchi
2023-08-23 17:07 ` [Intel-xe] [PATCH 03/42] drm/i915/cx0: Add intel_cx0_get_owned_lane_mask() Lucas De Marchi
2023-08-23 17:07 ` [Intel-xe] [PATCH 04/42] drm/i915: Simplify intel_cx0_program_phy_lane() with loop Lucas De Marchi
2023-08-23 17:07 ` [Intel-xe] [PATCH 05/42] drm/i915/cx0: Enable/disable TX only for owned PHY lanes Lucas De Marchi
2023-08-23 17:07 ` [Intel-xe] [PATCH 06/42] drm/i915/cx0: Program vswing only for owned lanes Lucas De Marchi
2023-08-23 17:07 ` [Intel-xe] [PATCH 07/42] drm/i915/tc: rename mtl_tc_port_get_pin_assignment_mask() Lucas De Marchi
2023-08-23 17:07 ` [Intel-xe] [PATCH 08/42] drm/i915/tc: make intel_tc_port_get_lane_mask() static Lucas De Marchi
2023-08-23 17:07 ` [Intel-xe] [PATCH 09/42] drm/i915/tc: move legacy code out of the main _max_lane_count() func Lucas De Marchi
2023-08-24 5:43 ` [Intel-xe] [Intel-gfx] " Kandpal, Suraj
2023-08-24 11:09 ` Coelho, Luciano
2023-08-24 15:08 ` Lucas De Marchi
2023-08-24 16:15 ` Kandpal, Suraj
2023-08-23 17:07 ` [Intel-xe] [PATCH 10/42] drm/i915/tc: remove "fia" from intel_tc_port_fia_max_lane_count() Lucas De Marchi
2023-08-24 5:47 ` [Intel-xe] [Intel-gfx] " Kandpal, Suraj
2023-08-23 17:07 ` [Intel-xe] [PATCH 11/42] drm/xe/lnl: Add IS_LUNARLAKE Lucas De Marchi
2023-08-23 17:55 ` Matt Roper
2023-08-24 15:32 ` Lucas De Marchi
2023-08-23 17:07 ` [Intel-xe] [PATCH 12/42] drm/i915/lnl: Add display definitions Lucas De Marchi
2023-08-23 18:03 ` Matt Roper
2023-08-24 8:20 ` Jani Nikula
2023-08-24 15:49 ` [Intel-xe] [Intel-gfx] " Lucas De Marchi
2023-08-24 15:58 ` Matt Roper
2023-08-23 17:07 ` [Intel-xe] [PATCH 13/42] drm/i915: Re-order if/else ladder in intel_detect_pch() Lucas De Marchi
2023-08-23 18:04 ` Matt Roper
2023-08-23 17:07 ` [Intel-xe] [PATCH 14/42] drm/i915/lnl: Add fake PCH Lucas De Marchi
2023-08-23 18:05 ` Matt Roper
2023-08-23 17:07 ` [Intel-xe] [PATCH 15/42] drm/i915/xe2lpd: Treat cursor plane as regular plane for DDB allocation Lucas De Marchi
2023-08-23 18:08 ` Matt Roper
2023-08-23 17:07 ` [Intel-xe] [PATCH 16/42] drm/i915/xe2lpd: Move D2D enable/disable Lucas De Marchi
2023-08-23 19:01 ` Matt Roper
2023-08-23 17:07 ` [Intel-xe] [PATCH 17/42] drm/i915/xe2lpd: D2D Enable preserve bits in DDI_BUF_CTL Lucas De Marchi
2023-08-24 8:25 ` Jani Nikula
2023-08-23 17:07 ` [Intel-xe] [PATCH 18/42] drm/i915/xe2lpd: Move registers to PICA Lucas De Marchi
2023-08-23 19:24 ` Matt Roper
2023-08-24 8:34 ` Jani Nikula
2023-08-24 10:34 ` Lucas De Marchi
2023-08-23 17:07 ` [Intel-xe] [PATCH 19/42] drm/i915/xe2lpd: Don't try to program PLANE_AUX_DIST Lucas De Marchi
2023-08-25 19:42 ` [Intel-xe] [Intel-gfx] " Srivatsa, Anusha
2023-08-23 17:07 ` [Intel-xe] [PATCH 20/42] drm/i915/xe2lpd: Register DE_RRMR has been removed Lucas De Marchi
2023-08-23 19:28 ` Matt Roper
2023-08-24 22:46 ` Lucas De Marchi
2023-08-23 17:07 ` [Intel-xe] [PATCH 21/42] drm/i915/xe2lpd: Add display power well Lucas De Marchi
2023-08-23 19:44 ` Matt Roper
2023-08-23 19:46 ` Matt Roper
2023-08-23 17:07 ` [Intel-xe] [PATCH 22/42] drm/i915/xe2lpd: Add DC state support Lucas De Marchi
2023-08-25 19:46 ` Srivatsa, Anusha
2023-08-23 17:07 ` [Intel-xe] [PATCH 23/42] drm/i915/xe2lpd: FBC is now supported on all pipes Lucas De Marchi
2023-08-23 19:49 ` Matt Roper
2023-08-24 15:53 ` Lucas De Marchi
2023-08-23 17:07 ` [Intel-xe] [PATCH 24/42] drm/i915/display: Remove FBC capability from fused off pipes Lucas De Marchi
2023-08-23 19:53 ` Matt Roper
2023-08-23 17:07 ` [Intel-xe] [PATCH 25/42] drm/i915/xe2lpd: Add support for DP aux channels Lucas De Marchi
2023-08-23 20:01 ` Matt Roper
2023-08-23 20:14 ` Lucas De Marchi
2023-08-23 17:07 ` [Intel-xe] [PATCH 26/42] drm/i915/xe2lpd: Handle port AUX interrupts Lucas De Marchi
2023-08-23 20:10 ` Matt Roper
2023-08-23 17:07 ` [Intel-xe] [PATCH 27/42] drm/i915/xe2lpd: Read pin assignment from IOM Lucas De Marchi
2023-08-23 20:28 ` Matt Roper
2023-08-24 11:31 ` Coelho, Luciano [this message]
2023-08-24 11:34 ` [Intel-xe] [Intel-gfx] " Coelho, Luciano
2023-08-24 15:06 ` Lucas De Marchi
2023-08-23 17:07 ` [Intel-xe] [PATCH 28/42] drm/i915/xe2lpd: enable odd size and panning for planar yuv on xe2lpd Lucas De Marchi
2023-08-24 5:26 ` Kandpal, Suraj
2023-08-23 17:07 ` [Intel-xe] [PATCH 29/42] drm/i915/xe2lpd: Add support for HPD Lucas De Marchi
2023-08-23 20:37 ` Matt Roper
2023-08-23 17:07 ` [Intel-xe] [PATCH 30/42] drm/i915/xe2lpd: Extend Wa_15010685871 Lucas De Marchi
2023-08-23 20:44 ` Matt Roper
2023-08-23 17:07 ` [Intel-xe] [PATCH 31/42] drm/i915/lnl: Add gmbus/ddc support Lucas De Marchi
2023-08-23 20:49 ` Matt Roper
2023-08-25 4:25 ` Lucas De Marchi
2023-08-25 21:55 ` Matt Roper
2023-08-25 22:36 ` Lucas De Marchi
2023-08-23 17:07 ` [Intel-xe] [PATCH 32/42] drm/i915/lnl: Introduce MDCLK Lucas De Marchi
2023-08-23 21:14 ` Matt Roper
2023-08-29 17:39 ` Lucas De Marchi
2023-08-23 17:07 ` [Intel-xe] [PATCH 33/42] drm/i915/lnl: Add CDCLK table Lucas De Marchi
2023-08-23 21:36 ` Matt Roper
2023-08-23 17:07 ` [Intel-xe] [PATCH 34/42] drm/i915/lnl: Start using CDCLK through PLL Lucas De Marchi
2023-08-23 22:01 ` Matt Roper
2023-08-29 18:45 ` Lucas De Marchi
2023-08-23 17:07 ` [Intel-xe] [PATCH 35/42] drm/i915/lnl: Introduce MDCLK_CDCLK ratio to DBuf Lucas De Marchi
2023-08-24 23:45 ` Matt Roper
2023-08-23 17:07 ` [Intel-xe] [PATCH 36/42] drm/i915/lnl: Add support for CDCLK initialization sequence Lucas De Marchi
2023-08-24 23:54 ` Matt Roper
2023-08-29 22:21 ` Lucas De Marchi
2023-08-23 17:07 ` [Intel-xe] [PATCH 37/42] drm/i915/xe2lpd: Write DBuf after CDCLK change in post plane Lucas De Marchi
2023-08-25 7:35 ` Kahola, Mika
2023-08-23 17:07 ` [Intel-xe] [PATCH 38/42] drm/i915/lnl: Serialize global state if mdclk/cdclk ratio changes Lucas De Marchi
2023-08-29 22:24 ` [Intel-xe] [Intel-gfx] " Lucas De Marchi
2023-08-23 17:07 ` [Intel-xe] [PATCH 39/42] drm/i915/lnl: Add pll table for LNL platform Lucas De Marchi
2023-08-25 0:06 ` Matt Roper
2023-08-23 17:07 ` [Intel-xe] [PATCH 40/42] drm/i915/lnl: Add support to check c10 phy link rate Lucas De Marchi
2023-08-25 0:07 ` Matt Roper
2023-08-23 17:07 ` [Intel-xe] [PATCH 41/42] drm/i915/xe2lpd: Update mbus on post plane updates Lucas De Marchi
2023-08-25 7:36 ` Kahola, Mika
2023-08-23 17:07 ` [Intel-xe] [PATCH 42/42] drm/xe/lnl: Enable the display support Lucas De Marchi
2023-08-25 0:13 ` Matt Roper
2023-08-23 17:12 ` [Intel-xe] ✓ CI.Patch_applied: success for Enable Lunar Lake display Patchwork
2023-08-23 17:12 ` [Intel-xe] ✗ CI.checkpatch: warning " Patchwork
2023-08-23 17:13 ` [Intel-xe] ✓ CI.KUnit: success " Patchwork
2023-08-23 17:17 ` [Intel-xe] ✓ CI.Build: " Patchwork
2023-08-23 17:18 ` [Intel-xe] ✓ CI.Hooks: " Patchwork
2023-08-23 17:18 ` [Intel-xe] ✗ CI.checksparse: warning " Patchwork
2023-08-23 17:46 ` [Intel-xe] ✓ CI.BAT: success " Patchwork
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