[PATCH v2 0/8] drm/i915: move more display dependencies from i915

[PATCH v2 0/8] drm/i915: move more display dependencies from i915

[Luca Coelho]

Hi,

This series continues my work of refactoring the clock gating
initialization, so that i915 doesn't do display-specific stuff.

With this, all register dependencies should be gone.

Changes in v2:
	* Removed #ifdef I915 from the header (Jani);
	* Removed BDW/HSW common function, keeping separate functions
          for each platform (Ville);
	* Handled WaKVMNotificationOnConfigChange:bdw as well (Ville);
	* Now we have 3 separate functions for BDW, we may want to
          combine them later (ignoring the order with non-display
          workarounds);

Please review.

Cheers,
Luca.


Luca Coelho (8):
  drm/i915: move SKL clock gating init to display
  drm/i915: move KBL clock gating init to display
  drm/i915/display: move CFL clock gating init to display
  drm/i915/display: move BXT clock gating init to display
  drm/i915/display: move GLK clock gating init to display
  drm/i915/display: move HSW and BDW clock gating init to display
  drm/i915/display: move pre-HSW clock gating init to display
  drm/i915: remove HAS_PCH_NOP() dependency from clock gating

 drivers/gpu/drm/i915/Makefile                 |   1 +
 .../i915/display/intel_display_clock_gating.c | 264 ++++++++++++++++++
 .../i915/display/intel_display_clock_gating.h |  27 ++
 .../gpu/drm/i915/display/intel_display_regs.h |   3 +
 drivers/gpu/drm/i915/intel_clock_gating.c     | 226 ++-------------
 5 files changed, 312 insertions(+), 209 deletions(-)
 create mode 100644 drivers/gpu/drm/i915/display/intel_display_clock_gating.c
 create mode 100644 drivers/gpu/drm/i915/display/intel_display_clock_gating.h

-- 
2.53.0

[PATCH v2 1/8] drm/i915: move SKL clock gating init to display

[Luca Coelho]

Move the SKL-specific display clock gating programming into a new file
inside display.

This removes dependency from intel_clock_gating.c to the display's
intel_pch.h file, so we can remove the include statement.

Signed-off-by: Luca Coelho <luciano.coelho@intel.com>
---
 drivers/gpu/drm/i915/Makefile                 |  1 +
 .../i915/display/intel_display_clock_gating.c | 19 +++++++++++++++++++
 .../i915/display/intel_display_clock_gating.h | 13 +++++++++++++
 drivers/gpu/drm/i915/intel_clock_gating.c     |  8 ++------
 4 files changed, 35 insertions(+), 6 deletions(-)
 create mode 100644 drivers/gpu/drm/i915/display/intel_display_clock_gating.c
 create mode 100644 drivers/gpu/drm/i915/display/intel_display_clock_gating.h

diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index b677720a1c2d..63a9e16826a9 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -255,6 +255,7 @@ i915-y += \
 	display/intel_cursor.o \
 	display/intel_dbuf_bw.o \
 	display/intel_de.o \
+	display/intel_display_clock_gating.o \
 	display/intel_display.o \
 	display/intel_display_conversion.o \
 	display/intel_display_driver.o \
diff --git a/drivers/gpu/drm/i915/display/intel_display_clock_gating.c b/drivers/gpu/drm/i915/display/intel_display_clock_gating.c
new file mode 100644
index 000000000000..4a94593335e0
--- /dev/null
+++ b/drivers/gpu/drm/i915/display/intel_display_clock_gating.c
@@ -0,0 +1,19 @@
+// SPDX-License-Identifier: MIT
+/*
+ * Copyright 2026 Intel Corporation
+ */
+
+#include <drm/intel/intel_gmd_misc_regs.h>
+
+#include "intel_de.h"
+#include "intel_display_clock_gating.h"
+#include "intel_display_regs.h"
+
+void intel_display_skl_init_clock_gating(struct intel_display *display)
+{
+	/*
+	 * WaFbcTurnOffFbcWatermark:skl
+	 * Display WA #0562: skl
+	 */
+	intel_de_rmw(display, DISP_ARB_CTL, 0, DISP_FBC_WM_DIS);
+}
diff --git a/drivers/gpu/drm/i915/display/intel_display_clock_gating.h b/drivers/gpu/drm/i915/display/intel_display_clock_gating.h
new file mode 100644
index 000000000000..00f416db7f47
--- /dev/null
+++ b/drivers/gpu/drm/i915/display/intel_display_clock_gating.h
@@ -0,0 +1,13 @@
+/* SPDX-License-Identifier: MIT */
+/*
+ * Copyright 2026 Intel Corporation
+ */
+
+#ifndef __INTEL_DISPLAY_CLOCK_GATING_H__
+#define __INTEL_DISPLAY_CLOCK_GATING_H__
+
+struct intel_display;
+
+void intel_display_skl_init_clock_gating(struct intel_display *display);
+
+#endif /* __INTEL_DISPLAY_CLOCK_GATING_H__ */
diff --git a/drivers/gpu/drm/i915/intel_clock_gating.c b/drivers/gpu/drm/i915/intel_clock_gating.c
index ee2489a2fbe7..454334fef5e7 100644
--- a/drivers/gpu/drm/i915/intel_clock_gating.c
+++ b/drivers/gpu/drm/i915/intel_clock_gating.c
@@ -31,9 +31,9 @@
 
 #include "display/i9xx_plane_regs.h"
 #include "display/intel_display.h"
+#include "display/intel_display_clock_gating.h"
 #include "display/intel_display_core.h"
 #include "display/intel_display_regs.h"
-#include "display/intel_pch.h"
 #include "gt/intel_engine_regs.h"
 #include "gt/intel_gt.h"
 #include "gt/intel_gt_mcr.h"
@@ -349,11 +349,7 @@ static void skl_init_clock_gating(struct drm_i915_private *i915)
 	/* WAC6entrylatency:skl */
 	intel_uncore_rmw(&i915->uncore, FBC_LLC_READ_CTRL, 0, FBC_LLC_FULLY_OPEN);
 
-	/*
-	 * WaFbcTurnOffFbcWatermark:skl
-	 * Display WA #0562: skl
-	 */
-	intel_uncore_rmw(&i915->uncore, DISP_ARB_CTL, 0, DISP_FBC_WM_DIS);
+	intel_display_skl_init_clock_gating(i915->display);
 }
 
 static void bdw_init_clock_gating(struct drm_i915_private *i915)
-- 
2.53.0

[PATCH v2 2/8] drm/i915: move KBL clock gating init to display

[Luca Coelho]

Move the KBL-specific display clock gating programming into a
display intel_display_clock_gating.c, to remove more dependencies from
i915 to display registers.

Signed-off-by: Luca Coelho <luciano.coelho@intel.com>
---
 .../gpu/drm/i915/display/intel_display_clock_gating.c    | 9 +++++++++
 .../gpu/drm/i915/display/intel_display_clock_gating.h    | 1 +
 drivers/gpu/drm/i915/intel_clock_gating.c                | 6 +-----
 3 files changed, 11 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display_clock_gating.c b/drivers/gpu/drm/i915/display/intel_display_clock_gating.c
index 4a94593335e0..508735212d6b 100644
--- a/drivers/gpu/drm/i915/display/intel_display_clock_gating.c
+++ b/drivers/gpu/drm/i915/display/intel_display_clock_gating.c
@@ -17,3 +17,12 @@ void intel_display_skl_init_clock_gating(struct intel_display *display)
 	 */
 	intel_de_rmw(display, DISP_ARB_CTL, 0, DISP_FBC_WM_DIS);
 }
+
+void intel_display_kbl_init_clock_gating(struct intel_display *display)
+{
+	/*
+	 * WaFbcTurnOffFbcWatermark:kbl
+	 * Display WA #0562: kbl
+	 */
+	intel_de_rmw(display, DISP_ARB_CTL, 0, DISP_FBC_WM_DIS);
+}
diff --git a/drivers/gpu/drm/i915/display/intel_display_clock_gating.h b/drivers/gpu/drm/i915/display/intel_display_clock_gating.h
index 00f416db7f47..8c21217de66a 100644
--- a/drivers/gpu/drm/i915/display/intel_display_clock_gating.h
+++ b/drivers/gpu/drm/i915/display/intel_display_clock_gating.h
@@ -9,5 +9,6 @@
 struct intel_display;
 
 void intel_display_skl_init_clock_gating(struct intel_display *display);
+void intel_display_kbl_init_clock_gating(struct intel_display *display);
 
 #endif /* __INTEL_DISPLAY_CLOCK_GATING_H__ */
diff --git a/drivers/gpu/drm/i915/intel_clock_gating.c b/drivers/gpu/drm/i915/intel_clock_gating.c
index 454334fef5e7..5f7910dbe164 100644
--- a/drivers/gpu/drm/i915/intel_clock_gating.c
+++ b/drivers/gpu/drm/i915/intel_clock_gating.c
@@ -331,11 +331,7 @@ static void kbl_init_clock_gating(struct drm_i915_private *i915)
 		intel_uncore_rmw(&i915->uncore, GEN6_UCGCTL1,
 				 0, GEN6_GAMUNIT_CLOCK_GATE_DISABLE);
 
-	/*
-	 * WaFbcTurnOffFbcWatermark:kbl
-	 * Display WA #0562: kbl
-	 */
-	intel_uncore_rmw(&i915->uncore, DISP_ARB_CTL, 0, DISP_FBC_WM_DIS);
+	intel_display_kbl_init_clock_gating(i915->display);
 }
 
 static void skl_init_clock_gating(struct drm_i915_private *i915)
-- 
2.53.0

[PATCH v2 3/8] drm/i915/display: move CFL clock gating init to display

[Luca Coelho]

Move the CFL/CML-specific display clock gating programming into
display intel_display_clock_gating.c, to remove more dependencies from
i915 to display registers.

Signed-off-by: Luca Coelho <luciano.coelho@intel.com>
---
 .../gpu/drm/i915/display/intel_display_clock_gating.c    | 9 +++++++++
 .../gpu/drm/i915/display/intel_display_clock_gating.h    | 1 +
 drivers/gpu/drm/i915/intel_clock_gating.c                | 6 +-----
 3 files changed, 11 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display_clock_gating.c b/drivers/gpu/drm/i915/display/intel_display_clock_gating.c
index 508735212d6b..82ea21d7377d 100644
--- a/drivers/gpu/drm/i915/display/intel_display_clock_gating.c
+++ b/drivers/gpu/drm/i915/display/intel_display_clock_gating.c
@@ -26,3 +26,12 @@ void intel_display_kbl_init_clock_gating(struct intel_display *display)
 	 */
 	intel_de_rmw(display, DISP_ARB_CTL, 0, DISP_FBC_WM_DIS);
 }
+
+void intel_display_cfl_init_clock_gating(struct intel_display *display)
+{
+	/*
+	 * WaFbcTurnOffFbcWatermark:cfl
+	 * Display WA #0562: cfl
+	 */
+	intel_de_rmw(display, DISP_ARB_CTL, 0, DISP_FBC_WM_DIS);
+}
diff --git a/drivers/gpu/drm/i915/display/intel_display_clock_gating.h b/drivers/gpu/drm/i915/display/intel_display_clock_gating.h
index 8c21217de66a..63960f1e80fc 100644
--- a/drivers/gpu/drm/i915/display/intel_display_clock_gating.h
+++ b/drivers/gpu/drm/i915/display/intel_display_clock_gating.h
@@ -10,5 +10,6 @@ struct intel_display;
 
 void intel_display_skl_init_clock_gating(struct intel_display *display);
 void intel_display_kbl_init_clock_gating(struct intel_display *display);
+void intel_display_cfl_init_clock_gating(struct intel_display *display);
 
 #endif /* __INTEL_DISPLAY_CLOCK_GATING_H__ */
diff --git a/drivers/gpu/drm/i915/intel_clock_gating.c b/drivers/gpu/drm/i915/intel_clock_gating.c
index 5f7910dbe164..b9bd23c2731e 100644
--- a/drivers/gpu/drm/i915/intel_clock_gating.c
+++ b/drivers/gpu/drm/i915/intel_clock_gating.c
@@ -307,11 +307,7 @@ static void cfl_init_clock_gating(struct drm_i915_private *i915)
 	/* WAC6entrylatency:cfl */
 	intel_uncore_rmw(&i915->uncore, FBC_LLC_READ_CTRL, 0, FBC_LLC_FULLY_OPEN);
 
-	/*
-	 * WaFbcTurnOffFbcWatermark:cfl
-	 * Display WA #0562: cfl
-	 */
-	intel_uncore_rmw(&i915->uncore, DISP_ARB_CTL, 0, DISP_FBC_WM_DIS);
+	intel_display_cfl_init_clock_gating(i915->display);
 }
 
 static void kbl_init_clock_gating(struct drm_i915_private *i915)
-- 
2.53.0

[PATCH v2 4/8] drm/i915/display: move BXT clock gating init to display

[Luca Coelho]

Move the BXT-specific display clock gating programming into display
intel_display_clock_gating.c, to remove more dependencies from i915.

Signed-off-by: Luca Coelho <luciano.coelho@intel.com>
---
 .../i915/display/intel_display_clock_gating.c | 25 +++++++++++++++++++
 .../i915/display/intel_display_clock_gating.h |  1 +
 drivers/gpu/drm/i915/intel_clock_gating.c     | 22 +---------------
 3 files changed, 27 insertions(+), 21 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display_clock_gating.c b/drivers/gpu/drm/i915/display/intel_display_clock_gating.c
index 82ea21d7377d..59041c807d6d 100644
--- a/drivers/gpu/drm/i915/display/intel_display_clock_gating.c
+++ b/drivers/gpu/drm/i915/display/intel_display_clock_gating.c
@@ -35,3 +35,28 @@ void intel_display_cfl_init_clock_gating(struct intel_display *display)
 	 */
 	intel_de_rmw(display, DISP_ARB_CTL, 0, DISP_FBC_WM_DIS);
 }
+
+void intel_display_bxt_init_clock_gating(struct intel_display *display)
+{
+	/*
+	 * Wa: Backlight PWM may stop in the asserted state, causing backlight
+	 * to stay fully on.
+	 */
+	intel_de_write(display, GEN9_CLKGATE_DIS_0,
+		       intel_de_read(display, GEN9_CLKGATE_DIS_0) |
+		       PWM1_GATING_DIS | PWM2_GATING_DIS);
+
+	/*
+	 * Lower the display internal timeout.
+	 * This is needed to avoid any hard hangs when DSI port PLL
+	 * is off and a MMIO access is attempted by any privilege
+	 * application, using batch buffers or any other means.
+	 */
+	intel_de_write(display, RM_TIMEOUT, MMIO_TIMEOUT_US(950));
+
+	/*
+	 * WaFbcTurnOffFbcWatermark:bxt
+	 * Display WA #0562: bxt
+	 */
+	intel_de_rmw(display, DISP_ARB_CTL, 0, DISP_FBC_WM_DIS);
+}
diff --git a/drivers/gpu/drm/i915/display/intel_display_clock_gating.h b/drivers/gpu/drm/i915/display/intel_display_clock_gating.h
index 63960f1e80fc..6bc84a9a4342 100644
--- a/drivers/gpu/drm/i915/display/intel_display_clock_gating.h
+++ b/drivers/gpu/drm/i915/display/intel_display_clock_gating.h
@@ -11,5 +11,6 @@ struct intel_display;
 void intel_display_skl_init_clock_gating(struct intel_display *display);
 void intel_display_kbl_init_clock_gating(struct intel_display *display);
 void intel_display_cfl_init_clock_gating(struct intel_display *display);
+void intel_display_bxt_init_clock_gating(struct intel_display *display);
 
 #endif /* __INTEL_DISPLAY_CLOCK_GATING_H__ */
diff --git a/drivers/gpu/drm/i915/intel_clock_gating.c b/drivers/gpu/drm/i915/intel_clock_gating.c
index b9bd23c2731e..4c1937d922b2 100644
--- a/drivers/gpu/drm/i915/intel_clock_gating.c
+++ b/drivers/gpu/drm/i915/intel_clock_gating.c
@@ -88,27 +88,7 @@ static void bxt_init_clock_gating(struct drm_i915_private *i915)
 	 */
 	intel_uncore_rmw(&i915->uncore, GEN8_UCGCTL6, 0, GEN8_HDCUNIT_CLOCK_GATE_DISABLE_HDCREQ);
 
-	/*
-	 * Wa: Backlight PWM may stop in the asserted state, causing backlight
-	 * to stay fully on.
-	 */
-	intel_uncore_write(&i915->uncore, GEN9_CLKGATE_DIS_0,
-			   intel_uncore_read(&i915->uncore, GEN9_CLKGATE_DIS_0) |
-			   PWM1_GATING_DIS | PWM2_GATING_DIS);
-
-	/*
-	 * Lower the display internal timeout.
-	 * This is needed to avoid any hard hangs when DSI port PLL
-	 * is off and a MMIO access is attempted by any privilege
-	 * application, using batch buffers or any other means.
-	 */
-	intel_uncore_write(&i915->uncore, RM_TIMEOUT, MMIO_TIMEOUT_US(950));
-
-	/*
-	 * WaFbcTurnOffFbcWatermark:bxt
-	 * Display WA #0562: bxt
-	 */
-	intel_uncore_rmw(&i915->uncore, DISP_ARB_CTL, 0, DISP_FBC_WM_DIS);
+	intel_display_bxt_init_clock_gating(i915->display);
 }
 
 static void glk_init_clock_gating(struct drm_i915_private *i915)
-- 
2.53.0

[PATCH v2 5/8] drm/i915/display: move GLK clock gating init to display

[Luca Coelho]

Move the GLK-specific display clock gating programming into display
intel_display_clock_gating.c, to remove more dependencies from i915 to
display registers.

Now that all remaining Gen9-family callers moved into display, we can
move the shared Gen9 display clock gating helper into display and
remove the old local helper from intel_clock_gating.c.

Signed-off-by: Luca Coelho <luciano.coelho@intel.com>
---
 .../i915/display/intel_display_clock_gating.c | 63 +++++++++++++++++++
 .../i915/display/intel_display_clock_gating.h |  1 +
 drivers/gpu/drm/i915/intel_clock_gating.c     | 44 +------------
 3 files changed, 65 insertions(+), 43 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display_clock_gating.c b/drivers/gpu/drm/i915/display/intel_display_clock_gating.c
index 59041c807d6d..e3b7522b4101 100644
--- a/drivers/gpu/drm/i915/display/intel_display_clock_gating.c
+++ b/drivers/gpu/drm/i915/display/intel_display_clock_gating.c
@@ -6,11 +6,46 @@
 #include <drm/intel/intel_gmd_misc_regs.h>
 
 #include "intel_de.h"
+#include "intel_display.h"
 #include "intel_display_clock_gating.h"
 #include "intel_display_regs.h"
 
+#include "i915_drv.h"
+
+static void intel_display_gen9_init_clock_gating(struct intel_display *display,
+						 bool has_llc)
+{
+	if (has_llc) {
+		/*
+		 * WaCompressedResourceDisplayNewHashMode:skl,kbl
+		 * Display WA #0390: skl,kbl
+		 *
+		 * Must match Sampler, Pixel Back End, and Media. See
+		 * WaCompressedResourceSamplerPbeMediaNewHashMode.
+		 */
+		intel_de_rmw(display, CHICKEN_PAR1_1, 0,
+			     SKL_DE_COMPRESSED_HASH_MODE);
+	}
+
+	/* See Bspec note for PSR2_CTL bit 31, Wa#828:skl,bxt,kbl,cfl */
+	intel_de_rmw(display, CHICKEN_PAR1_1, 0, SKL_EDP_PSR_FIX_RDWRAP);
+
+	/* WaEnableChickenDCPR:skl,bxt,kbl,glk,cfl */
+	intel_de_rmw(display, GEN8_CHICKEN_DCPR_1, 0, MASK_WAKEMEM);
+
+	/*
+	 * WaFbcWakeMemOn:skl,bxt,kbl,glk,cfl
+	 * Display WA #0859: skl,bxt,kbl,glk,cfl
+	 */
+	intel_de_rmw(display, DISP_ARB_CTL, 0, DISP_FBC_MEMORY_WAKE);
+}
+
 void intel_display_skl_init_clock_gating(struct intel_display *display)
 {
+	struct drm_i915_private *i915 = to_i915(display->drm);
+
+	intel_display_gen9_init_clock_gating(display, HAS_LLC(i915));
+
 	/*
 	 * WaFbcTurnOffFbcWatermark:skl
 	 * Display WA #0562: skl
@@ -20,6 +55,10 @@ void intel_display_skl_init_clock_gating(struct intel_display *display)
 
 void intel_display_kbl_init_clock_gating(struct intel_display *display)
 {
+	struct drm_i915_private *i915 = to_i915(display->drm);
+
+	intel_display_gen9_init_clock_gating(display, HAS_LLC(i915));
+
 	/*
 	 * WaFbcTurnOffFbcWatermark:kbl
 	 * Display WA #0562: kbl
@@ -29,6 +68,10 @@ void intel_display_kbl_init_clock_gating(struct intel_display *display)
 
 void intel_display_cfl_init_clock_gating(struct intel_display *display)
 {
+	struct drm_i915_private *i915 = to_i915(display->drm);
+
+	intel_display_gen9_init_clock_gating(display, HAS_LLC(i915));
+
 	/*
 	 * WaFbcTurnOffFbcWatermark:cfl
 	 * Display WA #0562: cfl
@@ -38,6 +81,10 @@ void intel_display_cfl_init_clock_gating(struct intel_display *display)
 
 void intel_display_bxt_init_clock_gating(struct intel_display *display)
 {
+	struct drm_i915_private *i915 = to_i915(display->drm);
+
+	intel_display_gen9_init_clock_gating(display, HAS_LLC(i915));
+
 	/*
 	 * Wa: Backlight PWM may stop in the asserted state, causing backlight
 	 * to stay fully on.
@@ -60,3 +107,19 @@ void intel_display_bxt_init_clock_gating(struct intel_display *display)
 	 */
 	intel_de_rmw(display, DISP_ARB_CTL, 0, DISP_FBC_WM_DIS);
 }
+
+void intel_display_glk_init_clock_gating(struct intel_display *display)
+{
+	struct drm_i915_private *i915 = to_i915(display->drm);
+
+	intel_display_gen9_init_clock_gating(display, HAS_LLC(i915));
+
+	/*
+	 * WaDisablePWMClockGating:glk
+	 * Backlight PWM may stop in the asserted state, causing backlight
+	 * to stay fully on.
+	 */
+	intel_de_write(display, GEN9_CLKGATE_DIS_0,
+		       intel_de_read(display, GEN9_CLKGATE_DIS_0) |
+		       PWM1_GATING_DIS | PWM2_GATING_DIS);
+}
diff --git a/drivers/gpu/drm/i915/display/intel_display_clock_gating.h b/drivers/gpu/drm/i915/display/intel_display_clock_gating.h
index 6bc84a9a4342..a7784db9d97a 100644
--- a/drivers/gpu/drm/i915/display/intel_display_clock_gating.h
+++ b/drivers/gpu/drm/i915/display/intel_display_clock_gating.h
@@ -12,5 +12,6 @@ void intel_display_skl_init_clock_gating(struct intel_display *display);
 void intel_display_kbl_init_clock_gating(struct intel_display *display);
 void intel_display_cfl_init_clock_gating(struct intel_display *display);
 void intel_display_bxt_init_clock_gating(struct intel_display *display);
+void intel_display_glk_init_clock_gating(struct intel_display *display);
 
 #endif /* __INTEL_DISPLAY_CLOCK_GATING_H__ */
diff --git a/drivers/gpu/drm/i915/intel_clock_gating.c b/drivers/gpu/drm/i915/intel_clock_gating.c
index 4c1937d922b2..777314e0c75d 100644
--- a/drivers/gpu/drm/i915/intel_clock_gating.c
+++ b/drivers/gpu/drm/i915/intel_clock_gating.c
@@ -49,36 +49,8 @@ struct drm_i915_clock_gating_funcs {
 	void (*init_clock_gating)(struct drm_i915_private *i915);
 };
 
-static void gen9_init_clock_gating(struct drm_i915_private *i915)
-{
-	if (HAS_LLC(i915)) {
-		/*
-		 * WaCompressedResourceDisplayNewHashMode:skl,kbl
-		 * Display WA #0390: skl,kbl
-		 *
-		 * Must match Sampler, Pixel Back End, and Media. See
-		 * WaCompressedResourceSamplerPbeMediaNewHashMode.
-		 */
-		intel_uncore_rmw(&i915->uncore, CHICKEN_PAR1_1, 0, SKL_DE_COMPRESSED_HASH_MODE);
-	}
-
-	/* See Bspec note for PSR2_CTL bit 31, Wa#828:skl,bxt,kbl,cfl */
-	intel_uncore_rmw(&i915->uncore, CHICKEN_PAR1_1, 0, SKL_EDP_PSR_FIX_RDWRAP);
-
-	/* WaEnableChickenDCPR:skl,bxt,kbl,glk,cfl */
-	intel_uncore_rmw(&i915->uncore, GEN8_CHICKEN_DCPR_1, 0, MASK_WAKEMEM);
-
-	/*
-	 * WaFbcWakeMemOn:skl,bxt,kbl,glk,cfl
-	 * Display WA #0859: skl,bxt,kbl,glk,cfl
-	 */
-	intel_uncore_rmw(&i915->uncore, DISP_ARB_CTL, 0, DISP_FBC_MEMORY_WAKE);
-}
-
 static void bxt_init_clock_gating(struct drm_i915_private *i915)
 {
-	gen9_init_clock_gating(i915);
-
 	/* WaDisableSDEUnitClockGating:bxt */
 	intel_uncore_rmw(&i915->uncore, GEN8_UCGCTL6, 0, GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
 
@@ -93,16 +65,7 @@ static void bxt_init_clock_gating(struct drm_i915_private *i915)
 
 static void glk_init_clock_gating(struct drm_i915_private *i915)
 {
-	gen9_init_clock_gating(i915);
-
-	/*
-	 * WaDisablePWMClockGating:glk
-	 * Backlight PWM may stop in the asserted state, causing backlight
-	 * to stay fully on.
-	 */
-	intel_uncore_write(&i915->uncore, GEN9_CLKGATE_DIS_0,
-			   intel_uncore_read(&i915->uncore, GEN9_CLKGATE_DIS_0) |
-			   PWM1_GATING_DIS | PWM2_GATING_DIS);
+	intel_display_glk_init_clock_gating(i915->display);
 }
 
 static void g4x_disable_trickle_feed(struct drm_i915_private *dev_priv)
@@ -282,7 +245,6 @@ static void dg2_init_clock_gating(struct drm_i915_private *i915)
 static void cfl_init_clock_gating(struct drm_i915_private *i915)
 {
 	intel_pch_init_clock_gating(i915->display);
-	gen9_init_clock_gating(i915);
 
 	/* WAC6entrylatency:cfl */
 	intel_uncore_rmw(&i915->uncore, FBC_LLC_READ_CTRL, 0, FBC_LLC_FULLY_OPEN);
@@ -292,8 +254,6 @@ static void cfl_init_clock_gating(struct drm_i915_private *i915)
 
 static void kbl_init_clock_gating(struct drm_i915_private *i915)
 {
-	gen9_init_clock_gating(i915);
-
 	/* WAC6entrylatency:kbl */
 	intel_uncore_rmw(&i915->uncore, FBC_LLC_READ_CTRL, 0, FBC_LLC_FULLY_OPEN);
 
@@ -312,8 +272,6 @@ static void kbl_init_clock_gating(struct drm_i915_private *i915)
 
 static void skl_init_clock_gating(struct drm_i915_private *i915)
 {
-	gen9_init_clock_gating(i915);
-
 	/* WaDisableDopClockGating:skl */
 	intel_uncore_rmw(&i915->uncore, GEN7_MISCCPCTL,
 			 GEN7_DOP_CLOCK_GATE_ENABLE, 0);
-- 
2.53.0

[PATCH v2 6/8] drm/i915/display: move HSW and BDW clock gating init to display

[Luca Coelho]

Move the HSW and BDW display clock gating programming into the display
code.  In this case we need two different helpers, because the common
code between these two is split in the middle.

Signed-off-by: Luca Coelho <luciano.coelho@intel.com>
---
 .../i915/display/intel_display_clock_gating.c | 44 +++++++++++++++++++
 .../i915/display/intel_display_clock_gating.h |  4 ++
 .../gpu/drm/i915/display/intel_display_regs.h |  3 ++
 drivers/gpu/drm/i915/intel_clock_gating.c     | 34 ++------------
 4 files changed, 55 insertions(+), 30 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display_clock_gating.c b/drivers/gpu/drm/i915/display/intel_display_clock_gating.c
index e3b7522b4101..d5085ce7adae 100644
--- a/drivers/gpu/drm/i915/display/intel_display_clock_gating.c
+++ b/drivers/gpu/drm/i915/display/intel_display_clock_gating.c
@@ -123,3 +123,47 @@ void intel_display_glk_init_clock_gating(struct intel_display *display)
 		       intel_de_read(display, GEN9_CLKGATE_DIS_0) |
 		       PWM1_GATING_DIS | PWM2_GATING_DIS);
 }
+
+void intel_display_bdw_clock_gating_disable_fbcq(struct intel_display *display)
+{
+	/* WaFbcAsynchFlipDisableFbcQueue:hsw,bdw */
+	intel_de_rmw(display, CHICKEN_PIPESL_1(PIPE_A), 0, HSW_FBCQ_DIS);
+}
+
+void intel_display_bdw_clock_gating_vblank_in_srd(struct intel_display *display)
+{
+	enum pipe pipe;
+
+	/* WaPsrDPAMaskVBlankInSRD:hsw */
+	intel_de_rmw(display, CHICKEN_PAR1_1, 0, HSW_MASK_VBL_TO_PIPE_IN_SRD);
+
+	for_each_pipe(display, pipe) {
+		/* WaPsrDPRSUnmaskVBlankInSRD:hsw,bdw */
+		intel_de_rmw(display, CHICKEN_PIPESL_1(pipe), 0,
+			     BDW_UNMASK_VBL_TO_REGS_IN_SRD);
+	}
+}
+
+void intel_display_bdw_clock_gating_kvm_notif(struct intel_display *display)
+{
+	/* WaKVMNotificationOnConfigChange:bdw */
+	intel_de_rmw(display, CHICKEN_PAR2_1, 0,
+		     KVM_CONFIG_CHANGE_NOTIFICATION_SELECT);
+}
+
+void intel_display_hsw_init_clock_gating(struct intel_display *display)
+{
+	enum pipe pipe;
+
+	/* WaFbcAsynchFlipDisableFbcQueue:hsw,bdw */
+	intel_de_rmw(display, CHICKEN_PIPESL_1(PIPE_A), 0, HSW_FBCQ_DIS);
+
+	/* WaPsrDPAMaskVBlankInSRD:hsw */
+	intel_de_rmw(display, CHICKEN_PAR1_1, 0, HSW_MASK_VBL_TO_PIPE_IN_SRD);
+
+	for_each_pipe(display, pipe) {
+		/* WaPsrDPRSUnmaskVBlankInSRD:hsw,bdw */
+		intel_de_rmw(display, CHICKEN_PIPESL_1(pipe), 0,
+			     HSW_UNMASK_VBL_TO_REGS_IN_SRD);
+	}
+}
diff --git a/drivers/gpu/drm/i915/display/intel_display_clock_gating.h b/drivers/gpu/drm/i915/display/intel_display_clock_gating.h
index a7784db9d97a..e0300dc8b041 100644
--- a/drivers/gpu/drm/i915/display/intel_display_clock_gating.h
+++ b/drivers/gpu/drm/i915/display/intel_display_clock_gating.h
@@ -13,5 +13,9 @@ void intel_display_kbl_init_clock_gating(struct intel_display *display);
 void intel_display_cfl_init_clock_gating(struct intel_display *display);
 void intel_display_bxt_init_clock_gating(struct intel_display *display);
 void intel_display_glk_init_clock_gating(struct intel_display *display);
+void intel_display_bdw_clock_gating_disable_fbcq(struct intel_display *display);
+void intel_display_bdw_clock_gating_vblank_in_srd(struct intel_display *display);
+void intel_display_bdw_clock_gating_kvm_notif(struct intel_display *display);
+void intel_display_hsw_init_clock_gating(struct intel_display *display);
 
 #endif /* __INTEL_DISPLAY_CLOCK_GATING_H__ */
diff --git a/drivers/gpu/drm/i915/display/intel_display_regs.h b/drivers/gpu/drm/i915/display/intel_display_regs.h
index 4746e9ebd920..fc9d3bbb921c 100644
--- a/drivers/gpu/drm/i915/display/intel_display_regs.h
+++ b/drivers/gpu/drm/i915/display/intel_display_regs.h
@@ -405,6 +405,9 @@
 #define   SKL_EDP_PSR_FIX_RDWRAP	REG_BIT(3)
 #define   IGNORE_PSR2_HW_TRACKING	REG_BIT(1)
 
+#define CHICKEN_PAR2_1		_MMIO(0x42090)
+#define   KVM_CONFIG_CHANGE_NOTIFICATION_SELECT	REG_BIT(14)
+
 /*
  * GEN9 clock gating regs
  */
diff --git a/drivers/gpu/drm/i915/intel_clock_gating.c b/drivers/gpu/drm/i915/intel_clock_gating.c
index 777314e0c75d..47b437a82f4e 100644
--- a/drivers/gpu/drm/i915/intel_clock_gating.c
+++ b/drivers/gpu/drm/i915/intel_clock_gating.c
@@ -284,23 +284,12 @@ static void skl_init_clock_gating(struct drm_i915_private *i915)
 
 static void bdw_init_clock_gating(struct drm_i915_private *i915)
 {
-	struct intel_display *display = i915->display;
-	enum pipe pipe;
-
-	/* WaFbcAsynchFlipDisableFbcQueue:hsw,bdw */
-	intel_uncore_rmw(&i915->uncore, CHICKEN_PIPESL_1(PIPE_A), 0, HSW_FBCQ_DIS);
+	intel_display_bdw_clock_gating_disable_fbcq(i915->display);
 
 	/* WaSwitchSolVfFArbitrationPriority:bdw */
 	intel_uncore_rmw(&i915->uncore, GAM_ECOCHK, 0, HSW_ECOCHK_ARB_PRIO_SOL);
 
-	/* WaPsrDPAMaskVBlankInSRD:bdw */
-	intel_uncore_rmw(&i915->uncore, CHICKEN_PAR1_1, 0, HSW_MASK_VBL_TO_PIPE_IN_SRD);
-
-	for_each_pipe(display, pipe) {
-		/* WaPsrDPRSUnmaskVBlankInSRD:bdw */
-		intel_uncore_rmw(&i915->uncore, CHICKEN_PIPESL_1(pipe),
-				 0, BDW_UNMASK_VBL_TO_REGS_IN_SRD);
-	}
+	intel_display_bdw_clock_gating_vblank_in_srd(i915->display);
 
 	/* WaVSRefCountFullforceMissDisable:bdw */
 	/* WaDSRefCountFullforceMissDisable:bdw */
@@ -316,9 +305,7 @@ static void bdw_init_clock_gating(struct drm_i915_private *i915)
 	/* WaProgramL3SqcReg1Default:bdw */
 	gen8_set_l3sqc_credits(i915, 30, 2);
 
-	/* WaKVMNotificationOnConfigChange:bdw */
-	intel_uncore_rmw(&i915->uncore, CHICKEN_PAR2_1,
-			 0, KVM_CONFIG_CHANGE_NOTIFICATION_SELECT);
+	intel_display_bdw_clock_gating_kvm_notif(i915->display);
 
 	intel_pch_init_clock_gating(i915->display);
 
@@ -332,20 +319,7 @@ static void bdw_init_clock_gating(struct drm_i915_private *i915)
 
 static void hsw_init_clock_gating(struct drm_i915_private *i915)
 {
-	struct intel_display *display = i915->display;
-	enum pipe pipe;
-
-	/* WaFbcAsynchFlipDisableFbcQueue:hsw,bdw */
-	intel_uncore_rmw(&i915->uncore, CHICKEN_PIPESL_1(PIPE_A), 0, HSW_FBCQ_DIS);
-
-	/* WaPsrDPAMaskVBlankInSRD:hsw */
-	intel_uncore_rmw(&i915->uncore, CHICKEN_PAR1_1, 0, HSW_MASK_VBL_TO_PIPE_IN_SRD);
-
-	for_each_pipe(display, pipe) {
-		/* WaPsrDPRSUnmaskVBlankInSRD:hsw */
-		intel_uncore_rmw(&i915->uncore, CHICKEN_PIPESL_1(pipe),
-				 0, HSW_UNMASK_VBL_TO_REGS_IN_SRD);
-	}
+	intel_display_hsw_init_clock_gating(i915->display);
 
 	/* This is required by WaCatErrorRejectionIssue:hsw */
 	intel_uncore_rmw(&i915->uncore, GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
-- 
2.53.0

[PATCH v2 7/8] drm/i915/display: move pre-HSW clock gating init to display

[Luca Coelho]

Move the remaining pre-HSW display clock gating programming into
display.

This also drops display register includes from intel_clock_gating.c.

Signed-off-by: Luca Coelho <luciano.coelho@intel.com>
---
 .../i915/display/intel_display_clock_gating.c |  95 ++++++++++++++++
 .../i915/display/intel_display_clock_gating.h |   6 +
 drivers/gpu/drm/i915/intel_clock_gating.c     | 103 +-----------------
 3 files changed, 107 insertions(+), 97 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display_clock_gating.c b/drivers/gpu/drm/i915/display/intel_display_clock_gating.c
index d5085ce7adae..6867963868a7 100644
--- a/drivers/gpu/drm/i915/display/intel_display_clock_gating.c
+++ b/drivers/gpu/drm/i915/display/intel_display_clock_gating.c
@@ -6,11 +6,13 @@
 #include <drm/intel/intel_gmd_misc_regs.h>
 
 #include "intel_de.h"
+#include "i9xx_plane_regs.h"
 #include "intel_display.h"
 #include "intel_display_clock_gating.h"
 #include "intel_display_regs.h"
 
 #include "i915_drv.h"
+#include "i915_reg.h"
 
 static void intel_display_gen9_init_clock_gating(struct intel_display *display,
 						 bool has_llc)
@@ -167,3 +169,96 @@ void intel_display_hsw_init_clock_gating(struct intel_display *display)
 			     HSW_UNMASK_VBL_TO_REGS_IN_SRD);
 	}
 }
+
+void intel_display_disable_trickle_feed(struct intel_display *display)
+{
+	enum pipe pipe;
+
+	for_each_pipe(display, pipe) {
+		intel_de_rmw(display, DSPCNTR(display, pipe), 0,
+			     DISP_TRICKLE_FEED_DISABLE);
+
+		intel_de_rmw(display, DSPSURF(display, pipe), 0, 0);
+		intel_de_posting_read(display, DSPSURF(display, pipe));
+	}
+}
+
+void intel_display_ilk_init_clock_gating(struct intel_display *display)
+{
+	struct drm_i915_private *i915 = to_i915(display->drm);
+	u32 dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE;
+
+	/*
+	 * Required for FBC
+	 * WaFbcDisableDpfcClockGating:ilk
+	 */
+	dspclk_gate |= ILK_DPFCRUNIT_CLOCK_GATE_DISABLE |
+		       ILK_DPFCUNIT_CLOCK_GATE_DISABLE |
+		       ILK_DPFDUNIT_CLOCK_GATE_ENABLE;
+
+	intel_de_write(display, ILK_DISPLAY_CHICKEN2,
+		       intel_de_read(display, ILK_DISPLAY_CHICKEN2) |
+		       ILK_DPARB_GATE | ILK_VSDPFD_FULL);
+	dspclk_gate |= ILK_DPARBUNIT_CLOCK_GATE_ENABLE;
+	intel_de_write(display, DISP_ARB_CTL,
+		       intel_de_read(display, DISP_ARB_CTL) |
+		       DISP_FBC_WM_DIS);
+
+	if (IS_IRONLAKE_M(i915)) {
+		/* WaFbcAsynchFlipDisableFbcQueue:ilk */
+		intel_de_rmw(display, ILK_DISPLAY_CHICKEN1, 0, ILK_FBCQ_DIS);
+		intel_de_rmw(display, ILK_DISPLAY_CHICKEN2, 0, ILK_DPARB_GATE);
+	}
+
+	intel_de_write(display, ILK_DSPCLK_GATE_D, dspclk_gate);
+	intel_de_rmw(display, ILK_DISPLAY_CHICKEN2, 0, ILK_ELPIN_409_SELECT);
+
+	intel_display_disable_trickle_feed(display);
+}
+
+void intel_display_gen6_init_clock_gating(struct intel_display *display)
+{
+	u32 dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE;
+
+	intel_de_write(display, ILK_DSPCLK_GATE_D, dspclk_gate);
+	intel_de_rmw(display, ILK_DISPLAY_CHICKEN2, 0, ILK_ELPIN_409_SELECT);
+
+	intel_de_write(display, ILK_DISPLAY_CHICKEN1,
+		       intel_de_read(display, ILK_DISPLAY_CHICKEN1) |
+		       ILK_FBCQ_DIS | ILK_PABSTRETCH_DIS);
+	intel_de_write(display, ILK_DISPLAY_CHICKEN2,
+		       intel_de_read(display, ILK_DISPLAY_CHICKEN2) |
+		       ILK_DPARB_GATE | ILK_VSDPFD_FULL);
+	intel_de_write(display, ILK_DSPCLK_GATE_D,
+		       intel_de_read(display, ILK_DSPCLK_GATE_D) |
+		       ILK_DPARBUNIT_CLOCK_GATE_ENABLE |
+		       ILK_DPFDUNIT_CLOCK_GATE_ENABLE);
+
+	intel_display_disable_trickle_feed(display);
+}
+
+void intel_display_ivb_init_clock_gating(struct intel_display *display)
+{
+	intel_de_write(display, ILK_DSPCLK_GATE_D, ILK_VRHUNIT_CLOCK_GATE_DISABLE);
+	intel_de_rmw(display, ILK_DISPLAY_CHICKEN1, 0, ILK_FBCQ_DIS);
+}
+
+void intel_display_g4x_init_clock_gating(struct intel_display *display)
+{
+	struct drm_i915_private *i915 = to_i915(display->drm);
+	u32 dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE |
+			  OVRUNIT_CLOCK_GATE_DISABLE |
+			  OVCUNIT_CLOCK_GATE_DISABLE;
+
+	if (IS_GM45(i915))
+		dspclk_gate |= DSSUNIT_CLOCK_GATE_DISABLE;
+
+	intel_de_write(display, DSPCLK_GATE_D, dspclk_gate);
+
+	intel_display_disable_trickle_feed(display);
+}
+
+void intel_display_i965gm_init_clock_gating(struct intel_display *display)
+{
+	intel_de_write(display, DSPCLK_GATE_D, 0);
+}
diff --git a/drivers/gpu/drm/i915/display/intel_display_clock_gating.h b/drivers/gpu/drm/i915/display/intel_display_clock_gating.h
index e0300dc8b041..b6dd34ca92dd 100644
--- a/drivers/gpu/drm/i915/display/intel_display_clock_gating.h
+++ b/drivers/gpu/drm/i915/display/intel_display_clock_gating.h
@@ -17,5 +17,11 @@ void intel_display_bdw_clock_gating_disable_fbcq(struct intel_display *display);
 void intel_display_bdw_clock_gating_vblank_in_srd(struct intel_display *display);
 void intel_display_bdw_clock_gating_kvm_notif(struct intel_display *display);
 void intel_display_hsw_init_clock_gating(struct intel_display *display);
+void intel_display_disable_trickle_feed(struct intel_display *display);
+void intel_display_ilk_init_clock_gating(struct intel_display *display);
+void intel_display_gen6_init_clock_gating(struct intel_display *display);
+void intel_display_ivb_init_clock_gating(struct intel_display *display);
+void intel_display_g4x_init_clock_gating(struct intel_display *display);
+void intel_display_i965gm_init_clock_gating(struct intel_display *display);
 
 #endif /* __INTEL_DISPLAY_CLOCK_GATING_H__ */
diff --git a/drivers/gpu/drm/i915/intel_clock_gating.c b/drivers/gpu/drm/i915/intel_clock_gating.c
index 47b437a82f4e..12559db84cf4 100644
--- a/drivers/gpu/drm/i915/intel_clock_gating.c
+++ b/drivers/gpu/drm/i915/intel_clock_gating.c
@@ -29,11 +29,8 @@
 #include <drm/intel/intel_gmd_misc_regs.h>
 #include <drm/intel/intel_gmd_interrupt_regs.h>
 
-#include "display/i9xx_plane_regs.h"
-#include "display/intel_display.h"
 #include "display/intel_display_clock_gating.h"
 #include "display/intel_display_core.h"
-#include "display/intel_display_regs.h"
 #include "gt/intel_engine_regs.h"
 #include "gt/intel_gt.h"
 #include "gt/intel_gt_mcr.h"
@@ -68,74 +65,15 @@ static void glk_init_clock_gating(struct drm_i915_private *i915)
 	intel_display_glk_init_clock_gating(i915->display);
 }
 
-static void g4x_disable_trickle_feed(struct drm_i915_private *dev_priv)
-{
-	struct intel_display *display = dev_priv->display;
-	enum pipe pipe;
-
-	for_each_pipe(display, pipe) {
-		intel_uncore_rmw(&dev_priv->uncore, DSPCNTR(display, pipe),
-				 0, DISP_TRICKLE_FEED_DISABLE);
-
-		intel_uncore_rmw(&dev_priv->uncore, DSPSURF(display, pipe),
-				 0, 0);
-		intel_uncore_posting_read(&dev_priv->uncore,
-					  DSPSURF(display, pipe));
-	}
-}
-
 static void ilk_init_clock_gating(struct drm_i915_private *i915)
 {
-	u32 dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE;
-
-	/*
-	 * Required for FBC
-	 * WaFbcDisableDpfcClockGating:ilk
-	 */
-	dspclk_gate |= ILK_DPFCRUNIT_CLOCK_GATE_DISABLE |
-		   ILK_DPFCUNIT_CLOCK_GATE_DISABLE |
-		   ILK_DPFDUNIT_CLOCK_GATE_ENABLE;
-
 	intel_uncore_write(&i915->uncore, PCH_3DCGDIS0,
 			   MARIUNIT_CLOCK_GATE_DISABLE |
 			   SVSMUNIT_CLOCK_GATE_DISABLE);
 	intel_uncore_write(&i915->uncore, PCH_3DCGDIS1,
 			   VFMUNIT_CLOCK_GATE_DISABLE);
 
-	/*
-	 * According to the spec the following bits should be set in
-	 * order to enable memory self-refresh
-	 * The bit 22/21 of 0x42004
-	 * The bit 5 of 0x42020
-	 * The bit 15 of 0x45000
-	 */
-	intel_uncore_write(&i915->uncore, ILK_DISPLAY_CHICKEN2,
-			   (intel_uncore_read(&i915->uncore, ILK_DISPLAY_CHICKEN2) |
-			    ILK_DPARB_GATE | ILK_VSDPFD_FULL));
-	dspclk_gate |= ILK_DPARBUNIT_CLOCK_GATE_ENABLE;
-	intel_uncore_write(&i915->uncore, DISP_ARB_CTL,
-			   (intel_uncore_read(&i915->uncore, DISP_ARB_CTL) |
-			    DISP_FBC_WM_DIS));
-
-	/*
-	 * Based on the document from hardware guys the following bits
-	 * should be set unconditionally in order to enable FBC.
-	 * The bit 22 of 0x42000
-	 * The bit 22 of 0x42004
-	 * The bit 7,8,9 of 0x42020.
-	 */
-	if (IS_IRONLAKE_M(i915)) {
-		/* WaFbcAsynchFlipDisableFbcQueue:ilk */
-		intel_uncore_rmw(&i915->uncore, ILK_DISPLAY_CHICKEN1, 0, ILK_FBCQ_DIS);
-		intel_uncore_rmw(&i915->uncore, ILK_DISPLAY_CHICKEN2, 0, ILK_DPARB_GATE);
-	}
-
-	intel_uncore_write(&i915->uncore, ILK_DSPCLK_GATE_D, dspclk_gate);
-
-	intel_uncore_rmw(&i915->uncore, ILK_DISPLAY_CHICKEN2, 0, ILK_ELPIN_409_SELECT);
-
-	g4x_disable_trickle_feed(i915);
-
+	intel_display_ilk_init_clock_gating(i915->display);
 	intel_pch_init_clock_gating(i915->display);
 }
 
@@ -152,11 +90,7 @@ static void gen6_check_mch_setup(struct drm_i915_private *i915)
 
 static void gen6_init_clock_gating(struct drm_i915_private *i915)
 {
-	u32 dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE;
-
-	intel_uncore_write(&i915->uncore, ILK_DSPCLK_GATE_D, dspclk_gate);
-
-	intel_uncore_rmw(&i915->uncore, ILK_DISPLAY_CHICKEN2, 0, ILK_ELPIN_409_SELECT);
+	intel_display_gen6_init_clock_gating(i915->display);
 
 	intel_uncore_write(&i915->uncore, GEN6_UCGCTL1,
 			   intel_uncore_read(&i915->uncore, GEN6_UCGCTL1) |
@@ -191,19 +125,6 @@ static void gen6_init_clock_gating(struct drm_i915_private *i915)
 	 *
 	 * WaFbcAsynchFlipDisableFbcQueue:snb
 	 */
-	intel_uncore_write(&i915->uncore, ILK_DISPLAY_CHICKEN1,
-			   intel_uncore_read(&i915->uncore, ILK_DISPLAY_CHICKEN1) |
-			   ILK_FBCQ_DIS | ILK_PABSTRETCH_DIS);
-	intel_uncore_write(&i915->uncore, ILK_DISPLAY_CHICKEN2,
-			   intel_uncore_read(&i915->uncore, ILK_DISPLAY_CHICKEN2) |
-			   ILK_DPARB_GATE | ILK_VSDPFD_FULL);
-	intel_uncore_write(&i915->uncore, ILK_DSPCLK_GATE_D,
-			   intel_uncore_read(&i915->uncore, ILK_DSPCLK_GATE_D) |
-			   ILK_DPARBUNIT_CLOCK_GATE_ENABLE  |
-			   ILK_DPFDUNIT_CLOCK_GATE_ENABLE);
-
-	g4x_disable_trickle_feed(i915);
-
 	intel_pch_init_clock_gating(i915->display);
 
 	gen6_check_mch_setup(i915);
@@ -335,10 +256,7 @@ static void ivb_init_clock_gating(struct drm_i915_private *i915)
 {
 	struct intel_display *display = i915->display;
 
-	intel_uncore_write(&i915->uncore, ILK_DSPCLK_GATE_D, ILK_VRHUNIT_CLOCK_GATE_DISABLE);
-
-	/* WaFbcAsynchFlipDisableFbcQueue:ivb */
-	intel_uncore_rmw(&i915->uncore, ILK_DISPLAY_CHICKEN1, 0, ILK_FBCQ_DIS);
+	intel_display_ivb_init_clock_gating(display);
 
 	/* WaDisableBackToBackFlipFix:ivb */
 	intel_uncore_write(&i915->uncore, IVB_CHICKEN3,
@@ -367,7 +285,7 @@ static void ivb_init_clock_gating(struct drm_i915_private *i915)
 	intel_uncore_rmw(&i915->uncore, GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
 			 0, GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
 
-	g4x_disable_trickle_feed(i915);
+	intel_display_disable_trickle_feed(display);
 
 	intel_uncore_rmw(&i915->uncore, GEN6_MBCUNIT_SNPCR, GEN6_MBC_SNPCR_MASK,
 			 GEN6_MBC_SNPCR_MED);
@@ -440,21 +358,12 @@ static void chv_init_clock_gating(struct drm_i915_private *i915)
 
 static void g4x_init_clock_gating(struct drm_i915_private *i915)
 {
-	u32 dspclk_gate;
-
 	intel_uncore_write(&i915->uncore, RENCLK_GATE_D1, 0);
 	intel_uncore_write(&i915->uncore, RENCLK_GATE_D2, VF_UNIT_CLOCK_GATE_DISABLE |
 			   GS_UNIT_CLOCK_GATE_DISABLE |
 			   CL_UNIT_CLOCK_GATE_DISABLE);
 	intel_uncore_write(&i915->uncore, RAMCLK_GATE_D, 0);
-	dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE |
-		OVRUNIT_CLOCK_GATE_DISABLE |
-		OVCUNIT_CLOCK_GATE_DISABLE;
-	if (IS_GM45(i915))
-		dspclk_gate |= DSSUNIT_CLOCK_GATE_DISABLE;
-	intel_uncore_write(&i915->uncore, DSPCLK_GATE_D, dspclk_gate);
-
-	g4x_disable_trickle_feed(i915);
+	intel_display_g4x_init_clock_gating(i915->display);
 }
 
 static void i965gm_init_clock_gating(struct drm_i915_private *i915)
@@ -463,7 +372,7 @@ static void i965gm_init_clock_gating(struct drm_i915_private *i915)
 
 	intel_uncore_write(uncore, RENCLK_GATE_D1, I965_RCC_CLOCK_GATE_DISABLE);
 	intel_uncore_write(uncore, RENCLK_GATE_D2, 0);
-	intel_uncore_write(uncore, DSPCLK_GATE_D, 0);
+	intel_display_i965gm_init_clock_gating(i915->display);
 	intel_uncore_write(uncore, RAMCLK_GATE_D, 0);
 	intel_uncore_write16(uncore, DEUC, 0);
 	intel_uncore_write(uncore,
-- 
2.53.0

[PATCH v2 8/8] drm/i915: remove HAS_PCH_NOP() dependency from clock gating

[Luca Coelho]

intel_pch_init_clock_gating() already handles unsupported PCH types,
including PCH_NOP, by doing nothing.

Drop the explicit HAS_PCH_NOP() check from the IVB clock gating
path and always call the display helper directly. This removes one
more direct dependency on display-side PCH macros from
intel_clock_gating.c.

Signed-off-by: Luca Coelho <luciano.coelho@intel.com>
---
 drivers/gpu/drm/i915/intel_clock_gating.c | 3 +--
 1 file changed, 1 insertion(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_clock_gating.c b/drivers/gpu/drm/i915/intel_clock_gating.c
index 12559db84cf4..d185199c43b8 100644
--- a/drivers/gpu/drm/i915/intel_clock_gating.c
+++ b/drivers/gpu/drm/i915/intel_clock_gating.c
@@ -290,8 +290,7 @@ static void ivb_init_clock_gating(struct drm_i915_private *i915)
 	intel_uncore_rmw(&i915->uncore, GEN6_MBCUNIT_SNPCR, GEN6_MBC_SNPCR_MASK,
 			 GEN6_MBC_SNPCR_MED);
 
-	if (!HAS_PCH_NOP(display))
-		intel_pch_init_clock_gating(display);
+	intel_pch_init_clock_gating(display);
 
 	gen6_check_mch_setup(i915);
 }
-- 
2.53.0

Re: [PATCH v2 5/8] drm/i915/display: move GLK clock gating init to display

[Jani Nikula]

On Tue, 31 Mar 2026, Luca Coelho <luciano.coelho@intel.com> wrote:
> Move the GLK-specific display clock gating programming into display
> intel_display_clock_gating.c, to remove more dependencies from i915 to
> display registers.
>
> Now that all remaining Gen9-family callers moved into display, we can
> move the shared Gen9 display clock gating helper into display and
> remove the old local helper from intel_clock_gating.c.
>
> Signed-off-by: Luca Coelho <luciano.coelho@intel.com>
> ---
>  .../i915/display/intel_display_clock_gating.c | 63 +++++++++++++++++++
>  .../i915/display/intel_display_clock_gating.h |  1 +
>  drivers/gpu/drm/i915/intel_clock_gating.c     | 44 +------------
>  3 files changed, 65 insertions(+), 43 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display_clock_gating.c b/drivers/gpu/drm/i915/display/intel_display_clock_gating.c
> index 59041c807d6d..e3b7522b4101 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_clock_gating.c
> +++ b/drivers/gpu/drm/i915/display/intel_display_clock_gating.c
> @@ -6,11 +6,46 @@
>  #include <drm/intel/intel_gmd_misc_regs.h>
>  
>  #include "intel_de.h"
> +#include "intel_display.h"
>  #include "intel_display_clock_gating.h"
>  #include "intel_display_regs.h"
>  
> +#include "i915_drv.h"

Nope, we can't do this anymore. Sorry for not noticing it in v1.

intel_display_clock_gating.c is something that should be built for both
i915 and xe, regardless of the platforms. And compat i915_drv.h doesn't
exist anymore for xe. We've removed that include from all the display
code. The only one remaining is intel_fb_pin.c, which is i915 specific
adaptation code that we'll also need to tackle soon.

Similarly, we can't use to_i915() or HAS_LLC() either.

I don't have an alternative suggestion right now, but this is what we
can't do. Sorry.


BR,
Jani.


> +
> +static void intel_display_gen9_init_clock_gating(struct intel_display *display,
> +						 bool has_llc)
> +{
> +	if (has_llc) {
> +		/*
> +		 * WaCompressedResourceDisplayNewHashMode:skl,kbl
> +		 * Display WA #0390: skl,kbl
> +		 *
> +		 * Must match Sampler, Pixel Back End, and Media. See
> +		 * WaCompressedResourceSamplerPbeMediaNewHashMode.
> +		 */
> +		intel_de_rmw(display, CHICKEN_PAR1_1, 0,
> +			     SKL_DE_COMPRESSED_HASH_MODE);
> +	}
> +
> +	/* See Bspec note for PSR2_CTL bit 31, Wa#828:skl,bxt,kbl,cfl */
> +	intel_de_rmw(display, CHICKEN_PAR1_1, 0, SKL_EDP_PSR_FIX_RDWRAP);
> +
> +	/* WaEnableChickenDCPR:skl,bxt,kbl,glk,cfl */
> +	intel_de_rmw(display, GEN8_CHICKEN_DCPR_1, 0, MASK_WAKEMEM);
> +
> +	/*
> +	 * WaFbcWakeMemOn:skl,bxt,kbl,glk,cfl
> +	 * Display WA #0859: skl,bxt,kbl,glk,cfl
> +	 */
> +	intel_de_rmw(display, DISP_ARB_CTL, 0, DISP_FBC_MEMORY_WAKE);
> +}
> +
>  void intel_display_skl_init_clock_gating(struct intel_display *display)
>  {
> +	struct drm_i915_private *i915 = to_i915(display->drm);
> +
> +	intel_display_gen9_init_clock_gating(display, HAS_LLC(i915));
> +
>  	/*
>  	 * WaFbcTurnOffFbcWatermark:skl
>  	 * Display WA #0562: skl
> @@ -20,6 +55,10 @@ void intel_display_skl_init_clock_gating(struct intel_display *display)
>  
>  void intel_display_kbl_init_clock_gating(struct intel_display *display)
>  {
> +	struct drm_i915_private *i915 = to_i915(display->drm);
> +
> +	intel_display_gen9_init_clock_gating(display, HAS_LLC(i915));
> +
>  	/*
>  	 * WaFbcTurnOffFbcWatermark:kbl
>  	 * Display WA #0562: kbl
> @@ -29,6 +68,10 @@ void intel_display_kbl_init_clock_gating(struct intel_display *display)
>  
>  void intel_display_cfl_init_clock_gating(struct intel_display *display)
>  {
> +	struct drm_i915_private *i915 = to_i915(display->drm);
> +
> +	intel_display_gen9_init_clock_gating(display, HAS_LLC(i915));
> +
>  	/*
>  	 * WaFbcTurnOffFbcWatermark:cfl
>  	 * Display WA #0562: cfl
> @@ -38,6 +81,10 @@ void intel_display_cfl_init_clock_gating(struct intel_display *display)
>  
>  void intel_display_bxt_init_clock_gating(struct intel_display *display)
>  {
> +	struct drm_i915_private *i915 = to_i915(display->drm);
> +
> +	intel_display_gen9_init_clock_gating(display, HAS_LLC(i915));
> +
>  	/*
>  	 * Wa: Backlight PWM may stop in the asserted state, causing backlight
>  	 * to stay fully on.
> @@ -60,3 +107,19 @@ void intel_display_bxt_init_clock_gating(struct intel_display *display)
>  	 */
>  	intel_de_rmw(display, DISP_ARB_CTL, 0, DISP_FBC_WM_DIS);
>  }
> +
> +void intel_display_glk_init_clock_gating(struct intel_display *display)
> +{
> +	struct drm_i915_private *i915 = to_i915(display->drm);
> +
> +	intel_display_gen9_init_clock_gating(display, HAS_LLC(i915));
> +
> +	/*
> +	 * WaDisablePWMClockGating:glk
> +	 * Backlight PWM may stop in the asserted state, causing backlight
> +	 * to stay fully on.
> +	 */
> +	intel_de_write(display, GEN9_CLKGATE_DIS_0,
> +		       intel_de_read(display, GEN9_CLKGATE_DIS_0) |
> +		       PWM1_GATING_DIS | PWM2_GATING_DIS);
> +}
> diff --git a/drivers/gpu/drm/i915/display/intel_display_clock_gating.h b/drivers/gpu/drm/i915/display/intel_display_clock_gating.h
> index 6bc84a9a4342..a7784db9d97a 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_clock_gating.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_clock_gating.h
> @@ -12,5 +12,6 @@ void intel_display_skl_init_clock_gating(struct intel_display *display);
>  void intel_display_kbl_init_clock_gating(struct intel_display *display);
>  void intel_display_cfl_init_clock_gating(struct intel_display *display);
>  void intel_display_bxt_init_clock_gating(struct intel_display *display);
> +void intel_display_glk_init_clock_gating(struct intel_display *display);
>  
>  #endif /* __INTEL_DISPLAY_CLOCK_GATING_H__ */
> diff --git a/drivers/gpu/drm/i915/intel_clock_gating.c b/drivers/gpu/drm/i915/intel_clock_gating.c
> index 4c1937d922b2..777314e0c75d 100644
> --- a/drivers/gpu/drm/i915/intel_clock_gating.c
> +++ b/drivers/gpu/drm/i915/intel_clock_gating.c
> @@ -49,36 +49,8 @@ struct drm_i915_clock_gating_funcs {
>  	void (*init_clock_gating)(struct drm_i915_private *i915);
>  };
>  
> -static void gen9_init_clock_gating(struct drm_i915_private *i915)
> -{
> -	if (HAS_LLC(i915)) {
> -		/*
> -		 * WaCompressedResourceDisplayNewHashMode:skl,kbl
> -		 * Display WA #0390: skl,kbl
> -		 *
> -		 * Must match Sampler, Pixel Back End, and Media. See
> -		 * WaCompressedResourceSamplerPbeMediaNewHashMode.
> -		 */
> -		intel_uncore_rmw(&i915->uncore, CHICKEN_PAR1_1, 0, SKL_DE_COMPRESSED_HASH_MODE);
> -	}
> -
> -	/* See Bspec note for PSR2_CTL bit 31, Wa#828:skl,bxt,kbl,cfl */
> -	intel_uncore_rmw(&i915->uncore, CHICKEN_PAR1_1, 0, SKL_EDP_PSR_FIX_RDWRAP);
> -
> -	/* WaEnableChickenDCPR:skl,bxt,kbl,glk,cfl */
> -	intel_uncore_rmw(&i915->uncore, GEN8_CHICKEN_DCPR_1, 0, MASK_WAKEMEM);
> -
> -	/*
> -	 * WaFbcWakeMemOn:skl,bxt,kbl,glk,cfl
> -	 * Display WA #0859: skl,bxt,kbl,glk,cfl
> -	 */
> -	intel_uncore_rmw(&i915->uncore, DISP_ARB_CTL, 0, DISP_FBC_MEMORY_WAKE);
> -}
> -
>  static void bxt_init_clock_gating(struct drm_i915_private *i915)
>  {
> -	gen9_init_clock_gating(i915);
> -
>  	/* WaDisableSDEUnitClockGating:bxt */
>  	intel_uncore_rmw(&i915->uncore, GEN8_UCGCTL6, 0, GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
>  
> @@ -93,16 +65,7 @@ static void bxt_init_clock_gating(struct drm_i915_private *i915)
>  
>  static void glk_init_clock_gating(struct drm_i915_private *i915)
>  {
> -	gen9_init_clock_gating(i915);
> -
> -	/*
> -	 * WaDisablePWMClockGating:glk
> -	 * Backlight PWM may stop in the asserted state, causing backlight
> -	 * to stay fully on.
> -	 */
> -	intel_uncore_write(&i915->uncore, GEN9_CLKGATE_DIS_0,
> -			   intel_uncore_read(&i915->uncore, GEN9_CLKGATE_DIS_0) |
> -			   PWM1_GATING_DIS | PWM2_GATING_DIS);
> +	intel_display_glk_init_clock_gating(i915->display);
>  }
>  
>  static void g4x_disable_trickle_feed(struct drm_i915_private *dev_priv)
> @@ -282,7 +245,6 @@ static void dg2_init_clock_gating(struct drm_i915_private *i915)
>  static void cfl_init_clock_gating(struct drm_i915_private *i915)
>  {
>  	intel_pch_init_clock_gating(i915->display);
> -	gen9_init_clock_gating(i915);
>  
>  	/* WAC6entrylatency:cfl */
>  	intel_uncore_rmw(&i915->uncore, FBC_LLC_READ_CTRL, 0, FBC_LLC_FULLY_OPEN);
> @@ -292,8 +254,6 @@ static void cfl_init_clock_gating(struct drm_i915_private *i915)
>  
>  static void kbl_init_clock_gating(struct drm_i915_private *i915)
>  {
> -	gen9_init_clock_gating(i915);
> -
>  	/* WAC6entrylatency:kbl */
>  	intel_uncore_rmw(&i915->uncore, FBC_LLC_READ_CTRL, 0, FBC_LLC_FULLY_OPEN);
>  
> @@ -312,8 +272,6 @@ static void kbl_init_clock_gating(struct drm_i915_private *i915)
>  
>  static void skl_init_clock_gating(struct drm_i915_private *i915)
>  {
> -	gen9_init_clock_gating(i915);
> -
>  	/* WaDisableDopClockGating:skl */
>  	intel_uncore_rmw(&i915->uncore, GEN7_MISCCPCTL,
>  			 GEN7_DOP_CLOCK_GATE_ENABLE, 0);

-- 
Jani Nikula, Intel

Re: [PATCH v2 7/8] drm/i915/display: move pre-HSW clock gating init to display

[Jani Nikula]

On Tue, 31 Mar 2026, Luca Coelho <luciano.coelho@intel.com> wrote:
> Move the remaining pre-HSW display clock gating programming into
> display.
>
> This also drops display register includes from intel_clock_gating.c.
>
> Signed-off-by: Luca Coelho <luciano.coelho@intel.com>
> ---
>  .../i915/display/intel_display_clock_gating.c |  95 ++++++++++++++++
>  .../i915/display/intel_display_clock_gating.h |   6 +
>  drivers/gpu/drm/i915/intel_clock_gating.c     | 103 +-----------------
>  3 files changed, 107 insertions(+), 97 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display_clock_gating.c b/drivers/gpu/drm/i915/display/intel_display_clock_gating.c
> index d5085ce7adae..6867963868a7 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_clock_gating.c
> +++ b/drivers/gpu/drm/i915/display/intel_display_clock_gating.c
> @@ -6,11 +6,13 @@
>  #include <drm/intel/intel_gmd_misc_regs.h>
>  
>  #include "intel_de.h"
> +#include "i9xx_plane_regs.h"
>  #include "intel_display.h"
>  #include "intel_display_clock_gating.h"
>  #include "intel_display_regs.h"
>  
>  #include "i915_drv.h"
> +#include "i915_reg.h"

Auch, another one I should've spotted in v1. We can't use i915_reg.h
either, we've already eradicated it from display code and xe compat
code.

If there are display registers still remaining in i915_reg.h, they need
to be moved to display headers.


BR,
Jani.

>  
>  static void intel_display_gen9_init_clock_gating(struct intel_display *display,
>  						 bool has_llc)
> @@ -167,3 +169,96 @@ void intel_display_hsw_init_clock_gating(struct intel_display *display)
>  			     HSW_UNMASK_VBL_TO_REGS_IN_SRD);
>  	}
>  }
> +
> +void intel_display_disable_trickle_feed(struct intel_display *display)
> +{
> +	enum pipe pipe;
> +
> +	for_each_pipe(display, pipe) {
> +		intel_de_rmw(display, DSPCNTR(display, pipe), 0,
> +			     DISP_TRICKLE_FEED_DISABLE);
> +
> +		intel_de_rmw(display, DSPSURF(display, pipe), 0, 0);
> +		intel_de_posting_read(display, DSPSURF(display, pipe));
> +	}
> +}
> +
> +void intel_display_ilk_init_clock_gating(struct intel_display *display)
> +{
> +	struct drm_i915_private *i915 = to_i915(display->drm);
> +	u32 dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE;
> +
> +	/*
> +	 * Required for FBC
> +	 * WaFbcDisableDpfcClockGating:ilk
> +	 */
> +	dspclk_gate |= ILK_DPFCRUNIT_CLOCK_GATE_DISABLE |
> +		       ILK_DPFCUNIT_CLOCK_GATE_DISABLE |
> +		       ILK_DPFDUNIT_CLOCK_GATE_ENABLE;
> +
> +	intel_de_write(display, ILK_DISPLAY_CHICKEN2,
> +		       intel_de_read(display, ILK_DISPLAY_CHICKEN2) |
> +		       ILK_DPARB_GATE | ILK_VSDPFD_FULL);
> +	dspclk_gate |= ILK_DPARBUNIT_CLOCK_GATE_ENABLE;
> +	intel_de_write(display, DISP_ARB_CTL,
> +		       intel_de_read(display, DISP_ARB_CTL) |
> +		       DISP_FBC_WM_DIS);
> +
> +	if (IS_IRONLAKE_M(i915)) {
> +		/* WaFbcAsynchFlipDisableFbcQueue:ilk */
> +		intel_de_rmw(display, ILK_DISPLAY_CHICKEN1, 0, ILK_FBCQ_DIS);
> +		intel_de_rmw(display, ILK_DISPLAY_CHICKEN2, 0, ILK_DPARB_GATE);
> +	}
> +
> +	intel_de_write(display, ILK_DSPCLK_GATE_D, dspclk_gate);
> +	intel_de_rmw(display, ILK_DISPLAY_CHICKEN2, 0, ILK_ELPIN_409_SELECT);
> +
> +	intel_display_disable_trickle_feed(display);
> +}
> +
> +void intel_display_gen6_init_clock_gating(struct intel_display *display)
> +{
> +	u32 dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE;
> +
> +	intel_de_write(display, ILK_DSPCLK_GATE_D, dspclk_gate);
> +	intel_de_rmw(display, ILK_DISPLAY_CHICKEN2, 0, ILK_ELPIN_409_SELECT);
> +
> +	intel_de_write(display, ILK_DISPLAY_CHICKEN1,
> +		       intel_de_read(display, ILK_DISPLAY_CHICKEN1) |
> +		       ILK_FBCQ_DIS | ILK_PABSTRETCH_DIS);
> +	intel_de_write(display, ILK_DISPLAY_CHICKEN2,
> +		       intel_de_read(display, ILK_DISPLAY_CHICKEN2) |
> +		       ILK_DPARB_GATE | ILK_VSDPFD_FULL);
> +	intel_de_write(display, ILK_DSPCLK_GATE_D,
> +		       intel_de_read(display, ILK_DSPCLK_GATE_D) |
> +		       ILK_DPARBUNIT_CLOCK_GATE_ENABLE |
> +		       ILK_DPFDUNIT_CLOCK_GATE_ENABLE);
> +
> +	intel_display_disable_trickle_feed(display);
> +}
> +
> +void intel_display_ivb_init_clock_gating(struct intel_display *display)
> +{
> +	intel_de_write(display, ILK_DSPCLK_GATE_D, ILK_VRHUNIT_CLOCK_GATE_DISABLE);
> +	intel_de_rmw(display, ILK_DISPLAY_CHICKEN1, 0, ILK_FBCQ_DIS);
> +}
> +
> +void intel_display_g4x_init_clock_gating(struct intel_display *display)
> +{
> +	struct drm_i915_private *i915 = to_i915(display->drm);
> +	u32 dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE |
> +			  OVRUNIT_CLOCK_GATE_DISABLE |
> +			  OVCUNIT_CLOCK_GATE_DISABLE;
> +
> +	if (IS_GM45(i915))
> +		dspclk_gate |= DSSUNIT_CLOCK_GATE_DISABLE;
> +
> +	intel_de_write(display, DSPCLK_GATE_D, dspclk_gate);
> +
> +	intel_display_disable_trickle_feed(display);
> +}
> +
> +void intel_display_i965gm_init_clock_gating(struct intel_display *display)
> +{
> +	intel_de_write(display, DSPCLK_GATE_D, 0);
> +}
> diff --git a/drivers/gpu/drm/i915/display/intel_display_clock_gating.h b/drivers/gpu/drm/i915/display/intel_display_clock_gating.h
> index e0300dc8b041..b6dd34ca92dd 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_clock_gating.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_clock_gating.h
> @@ -17,5 +17,11 @@ void intel_display_bdw_clock_gating_disable_fbcq(struct intel_display *display);
>  void intel_display_bdw_clock_gating_vblank_in_srd(struct intel_display *display);
>  void intel_display_bdw_clock_gating_kvm_notif(struct intel_display *display);
>  void intel_display_hsw_init_clock_gating(struct intel_display *display);
> +void intel_display_disable_trickle_feed(struct intel_display *display);
> +void intel_display_ilk_init_clock_gating(struct intel_display *display);
> +void intel_display_gen6_init_clock_gating(struct intel_display *display);
> +void intel_display_ivb_init_clock_gating(struct intel_display *display);
> +void intel_display_g4x_init_clock_gating(struct intel_display *display);
> +void intel_display_i965gm_init_clock_gating(struct intel_display *display);
>  
>  #endif /* __INTEL_DISPLAY_CLOCK_GATING_H__ */
> diff --git a/drivers/gpu/drm/i915/intel_clock_gating.c b/drivers/gpu/drm/i915/intel_clock_gating.c
> index 47b437a82f4e..12559db84cf4 100644
> --- a/drivers/gpu/drm/i915/intel_clock_gating.c
> +++ b/drivers/gpu/drm/i915/intel_clock_gating.c
> @@ -29,11 +29,8 @@
>  #include <drm/intel/intel_gmd_misc_regs.h>
>  #include <drm/intel/intel_gmd_interrupt_regs.h>
>  
> -#include "display/i9xx_plane_regs.h"
> -#include "display/intel_display.h"
>  #include "display/intel_display_clock_gating.h"
>  #include "display/intel_display_core.h"
> -#include "display/intel_display_regs.h"
>  #include "gt/intel_engine_regs.h"
>  #include "gt/intel_gt.h"
>  #include "gt/intel_gt_mcr.h"
> @@ -68,74 +65,15 @@ static void glk_init_clock_gating(struct drm_i915_private *i915)
>  	intel_display_glk_init_clock_gating(i915->display);
>  }
>  
> -static void g4x_disable_trickle_feed(struct drm_i915_private *dev_priv)
> -{
> -	struct intel_display *display = dev_priv->display;
> -	enum pipe pipe;
> -
> -	for_each_pipe(display, pipe) {
> -		intel_uncore_rmw(&dev_priv->uncore, DSPCNTR(display, pipe),
> -				 0, DISP_TRICKLE_FEED_DISABLE);
> -
> -		intel_uncore_rmw(&dev_priv->uncore, DSPSURF(display, pipe),
> -				 0, 0);
> -		intel_uncore_posting_read(&dev_priv->uncore,
> -					  DSPSURF(display, pipe));
> -	}
> -}
> -
>  static void ilk_init_clock_gating(struct drm_i915_private *i915)
>  {
> -	u32 dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE;
> -
> -	/*
> -	 * Required for FBC
> -	 * WaFbcDisableDpfcClockGating:ilk
> -	 */
> -	dspclk_gate |= ILK_DPFCRUNIT_CLOCK_GATE_DISABLE |
> -		   ILK_DPFCUNIT_CLOCK_GATE_DISABLE |
> -		   ILK_DPFDUNIT_CLOCK_GATE_ENABLE;
> -
>  	intel_uncore_write(&i915->uncore, PCH_3DCGDIS0,
>  			   MARIUNIT_CLOCK_GATE_DISABLE |
>  			   SVSMUNIT_CLOCK_GATE_DISABLE);
>  	intel_uncore_write(&i915->uncore, PCH_3DCGDIS1,
>  			   VFMUNIT_CLOCK_GATE_DISABLE);
>  
> -	/*
> -	 * According to the spec the following bits should be set in
> -	 * order to enable memory self-refresh
> -	 * The bit 22/21 of 0x42004
> -	 * The bit 5 of 0x42020
> -	 * The bit 15 of 0x45000
> -	 */
> -	intel_uncore_write(&i915->uncore, ILK_DISPLAY_CHICKEN2,
> -			   (intel_uncore_read(&i915->uncore, ILK_DISPLAY_CHICKEN2) |
> -			    ILK_DPARB_GATE | ILK_VSDPFD_FULL));
> -	dspclk_gate |= ILK_DPARBUNIT_CLOCK_GATE_ENABLE;
> -	intel_uncore_write(&i915->uncore, DISP_ARB_CTL,
> -			   (intel_uncore_read(&i915->uncore, DISP_ARB_CTL) |
> -			    DISP_FBC_WM_DIS));
> -
> -	/*
> -	 * Based on the document from hardware guys the following bits
> -	 * should be set unconditionally in order to enable FBC.
> -	 * The bit 22 of 0x42000
> -	 * The bit 22 of 0x42004
> -	 * The bit 7,8,9 of 0x42020.
> -	 */
> -	if (IS_IRONLAKE_M(i915)) {
> -		/* WaFbcAsynchFlipDisableFbcQueue:ilk */
> -		intel_uncore_rmw(&i915->uncore, ILK_DISPLAY_CHICKEN1, 0, ILK_FBCQ_DIS);
> -		intel_uncore_rmw(&i915->uncore, ILK_DISPLAY_CHICKEN2, 0, ILK_DPARB_GATE);
> -	}
> -
> -	intel_uncore_write(&i915->uncore, ILK_DSPCLK_GATE_D, dspclk_gate);
> -
> -	intel_uncore_rmw(&i915->uncore, ILK_DISPLAY_CHICKEN2, 0, ILK_ELPIN_409_SELECT);
> -
> -	g4x_disable_trickle_feed(i915);
> -
> +	intel_display_ilk_init_clock_gating(i915->display);
>  	intel_pch_init_clock_gating(i915->display);
>  }
>  
> @@ -152,11 +90,7 @@ static void gen6_check_mch_setup(struct drm_i915_private *i915)
>  
>  static void gen6_init_clock_gating(struct drm_i915_private *i915)
>  {
> -	u32 dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE;
> -
> -	intel_uncore_write(&i915->uncore, ILK_DSPCLK_GATE_D, dspclk_gate);
> -
> -	intel_uncore_rmw(&i915->uncore, ILK_DISPLAY_CHICKEN2, 0, ILK_ELPIN_409_SELECT);
> +	intel_display_gen6_init_clock_gating(i915->display);
>  
>  	intel_uncore_write(&i915->uncore, GEN6_UCGCTL1,
>  			   intel_uncore_read(&i915->uncore, GEN6_UCGCTL1) |
> @@ -191,19 +125,6 @@ static void gen6_init_clock_gating(struct drm_i915_private *i915)
>  	 *
>  	 * WaFbcAsynchFlipDisableFbcQueue:snb
>  	 */
> -	intel_uncore_write(&i915->uncore, ILK_DISPLAY_CHICKEN1,
> -			   intel_uncore_read(&i915->uncore, ILK_DISPLAY_CHICKEN1) |
> -			   ILK_FBCQ_DIS | ILK_PABSTRETCH_DIS);
> -	intel_uncore_write(&i915->uncore, ILK_DISPLAY_CHICKEN2,
> -			   intel_uncore_read(&i915->uncore, ILK_DISPLAY_CHICKEN2) |
> -			   ILK_DPARB_GATE | ILK_VSDPFD_FULL);
> -	intel_uncore_write(&i915->uncore, ILK_DSPCLK_GATE_D,
> -			   intel_uncore_read(&i915->uncore, ILK_DSPCLK_GATE_D) |
> -			   ILK_DPARBUNIT_CLOCK_GATE_ENABLE  |
> -			   ILK_DPFDUNIT_CLOCK_GATE_ENABLE);
> -
> -	g4x_disable_trickle_feed(i915);
> -
>  	intel_pch_init_clock_gating(i915->display);
>  
>  	gen6_check_mch_setup(i915);
> @@ -335,10 +256,7 @@ static void ivb_init_clock_gating(struct drm_i915_private *i915)
>  {
>  	struct intel_display *display = i915->display;
>  
> -	intel_uncore_write(&i915->uncore, ILK_DSPCLK_GATE_D, ILK_VRHUNIT_CLOCK_GATE_DISABLE);
> -
> -	/* WaFbcAsynchFlipDisableFbcQueue:ivb */
> -	intel_uncore_rmw(&i915->uncore, ILK_DISPLAY_CHICKEN1, 0, ILK_FBCQ_DIS);
> +	intel_display_ivb_init_clock_gating(display);
>  
>  	/* WaDisableBackToBackFlipFix:ivb */
>  	intel_uncore_write(&i915->uncore, IVB_CHICKEN3,
> @@ -367,7 +285,7 @@ static void ivb_init_clock_gating(struct drm_i915_private *i915)
>  	intel_uncore_rmw(&i915->uncore, GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
>  			 0, GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
>  
> -	g4x_disable_trickle_feed(i915);
> +	intel_display_disable_trickle_feed(display);
>  
>  	intel_uncore_rmw(&i915->uncore, GEN6_MBCUNIT_SNPCR, GEN6_MBC_SNPCR_MASK,
>  			 GEN6_MBC_SNPCR_MED);
> @@ -440,21 +358,12 @@ static void chv_init_clock_gating(struct drm_i915_private *i915)
>  
>  static void g4x_init_clock_gating(struct drm_i915_private *i915)
>  {
> -	u32 dspclk_gate;
> -
>  	intel_uncore_write(&i915->uncore, RENCLK_GATE_D1, 0);
>  	intel_uncore_write(&i915->uncore, RENCLK_GATE_D2, VF_UNIT_CLOCK_GATE_DISABLE |
>  			   GS_UNIT_CLOCK_GATE_DISABLE |
>  			   CL_UNIT_CLOCK_GATE_DISABLE);
>  	intel_uncore_write(&i915->uncore, RAMCLK_GATE_D, 0);
> -	dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE |
> -		OVRUNIT_CLOCK_GATE_DISABLE |
> -		OVCUNIT_CLOCK_GATE_DISABLE;
> -	if (IS_GM45(i915))
> -		dspclk_gate |= DSSUNIT_CLOCK_GATE_DISABLE;
> -	intel_uncore_write(&i915->uncore, DSPCLK_GATE_D, dspclk_gate);
> -
> -	g4x_disable_trickle_feed(i915);
> +	intel_display_g4x_init_clock_gating(i915->display);
>  }
>  
>  static void i965gm_init_clock_gating(struct drm_i915_private *i915)
> @@ -463,7 +372,7 @@ static void i965gm_init_clock_gating(struct drm_i915_private *i915)
>  
>  	intel_uncore_write(uncore, RENCLK_GATE_D1, I965_RCC_CLOCK_GATE_DISABLE);
>  	intel_uncore_write(uncore, RENCLK_GATE_D2, 0);
> -	intel_uncore_write(uncore, DSPCLK_GATE_D, 0);
> +	intel_display_i965gm_init_clock_gating(i915->display);
>  	intel_uncore_write(uncore, RAMCLK_GATE_D, 0);
>  	intel_uncore_write16(uncore, DEUC, 0);
>  	intel_uncore_write(uncore,

-- 
Jani Nikula, Intel

✗ CI.checkpatch: warning for drm/i915: move more display dependencies from i915 (rev2)

[Patchwork]

== Series Details ==

Series: drm/i915: move more display dependencies from i915 (rev2)
URL   : https://patchwork.freedesktop.org/series/163785/
State : warning

== Summary ==

+ KERNEL=/kernel
+ git clone https://gitlab.freedesktop.org/drm/maintainer-tools mt
Cloning into 'mt'...
warning: redirecting to https://gitlab.freedesktop.org/drm/maintainer-tools.git/
+ git -C mt rev-list -n1 origin/master
1f57ba1afceae32108bd24770069f764d940a0e4
+ cd /kernel
+ git config --global --add safe.directory /kernel
+ git log -n1
commit ed1e8287c9e24b5e963c4dd74bec7d017ad27f3b
Author: Luca Coelho <luciano.coelho@intel.com>
Date:   Tue Mar 31 15:07:19 2026 +0300

    drm/i915: remove HAS_PCH_NOP() dependency from clock gating
    
    intel_pch_init_clock_gating() already handles unsupported PCH types,
    including PCH_NOP, by doing nothing.
    
    Drop the explicit HAS_PCH_NOP() check from the IVB clock gating
    path and always call the display helper directly. This removes one
    more direct dependency on display-side PCH macros from
    intel_clock_gating.c.
    
    Signed-off-by: Luca Coelho <luciano.coelho@intel.com>
+ /mt/dim checkpatch 2ca39f35278e7f6e1750c710e75c32172fb1aa11 drm-intel
eda8382377c5 drm/i915: move SKL clock gating init to display
-:27: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does MAINTAINERS need updating?
#27: 
new file mode 100644

total: 0 errors, 1 warnings, 0 checks, 61 lines checked
d109031a91cc drm/i915: move KBL clock gating init to display
d52e5d266b92 drm/i915/display: move CFL clock gating init to display
b1ec236f4b6f drm/i915/display: move BXT clock gating init to display
b8cc33ab3806 drm/i915/display: move GLK clock gating init to display
c6bc88d99314 drm/i915/display: move HSW and BDW clock gating init to display
ec6056271acb drm/i915/display: move pre-HSW clock gating init to display
ed1e8287c9e2 drm/i915: remove HAS_PCH_NOP() dependency from clock gating

✓ CI.KUnit: success for drm/i915: move more display dependencies from i915 (rev2)

[Patchwork]

== Series Details ==

Series: drm/i915: move more display dependencies from i915 (rev2)
URL   : https://patchwork.freedesktop.org/series/163785/
State : success

== Summary ==

+ trap cleanup EXIT
+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/xe/.kunitconfig
[07:04:39] Configuring KUnit Kernel ...
Generating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[07:04:43] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[07:05:14] Starting KUnit Kernel (1/1)...
[07:05:14] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[07:05:15] ================== guc_buf (11 subtests) ===================
[07:05:15] [PASSED] test_smallest
[07:05:15] [PASSED] test_largest
[07:05:15] [PASSED] test_granular
[07:05:15] [PASSED] test_unique
[07:05:15] [PASSED] test_overlap
[07:05:15] [PASSED] test_reusable
[07:05:15] [PASSED] test_too_big
[07:05:15] [PASSED] test_flush
[07:05:15] [PASSED] test_lookup
[07:05:15] [PASSED] test_data
[07:05:15] [PASSED] test_class
[07:05:15] ===================== [PASSED] guc_buf =====================
[07:05:15] =================== guc_dbm (7 subtests) ===================
[07:05:15] [PASSED] test_empty
[07:05:15] [PASSED] test_default
[07:05:15] ======================== test_size  ========================
[07:05:15] [PASSED] 4
[07:05:15] [PASSED] 8
[07:05:15] [PASSED] 32
[07:05:15] [PASSED] 256
[07:05:15] ==================== [PASSED] test_size ====================
[07:05:15] ======================= test_reuse  ========================
[07:05:15] [PASSED] 4
[07:05:15] [PASSED] 8
[07:05:15] [PASSED] 32
[07:05:15] [PASSED] 256
[07:05:15] =================== [PASSED] test_reuse ====================
[07:05:15] =================== test_range_overlap  ====================
[07:05:15] [PASSED] 4
[07:05:15] [PASSED] 8
[07:05:15] [PASSED] 32
[07:05:15] [PASSED] 256
[07:05:15] =============== [PASSED] test_range_overlap ================
[07:05:15] =================== test_range_compact  ====================
[07:05:15] [PASSED] 4
[07:05:15] [PASSED] 8
[07:05:15] [PASSED] 32
[07:05:15] [PASSED] 256
[07:05:15] =============== [PASSED] test_range_compact ================
[07:05:15] ==================== test_range_spare  =====================
[07:05:15] [PASSED] 4
[07:05:15] [PASSED] 8
[07:05:15] [PASSED] 32
[07:05:15] [PASSED] 256
[07:05:15] ================ [PASSED] test_range_spare =================
[07:05:15] ===================== [PASSED] guc_dbm =====================
[07:05:15] =================== guc_idm (6 subtests) ===================
[07:05:15] [PASSED] bad_init
[07:05:15] [PASSED] no_init
[07:05:15] [PASSED] init_fini
[07:05:15] [PASSED] check_used
[07:05:15] [PASSED] check_quota
[07:05:15] [PASSED] check_all
[07:05:15] ===================== [PASSED] guc_idm =====================
[07:05:15] ================== no_relay (3 subtests) ===================
[07:05:15] [PASSED] xe_drops_guc2pf_if_not_ready
[07:05:15] [PASSED] xe_drops_guc2vf_if_not_ready
[07:05:15] [PASSED] xe_rejects_send_if_not_ready
[07:05:15] ==================== [PASSED] no_relay =====================
[07:05:15] ================== pf_relay (14 subtests) ==================
[07:05:15] [PASSED] pf_rejects_guc2pf_too_short
[07:05:15] [PASSED] pf_rejects_guc2pf_too_long
[07:05:15] [PASSED] pf_rejects_guc2pf_no_payload
[07:05:15] [PASSED] pf_fails_no_payload
[07:05:15] [PASSED] pf_fails_bad_origin
[07:05:15] [PASSED] pf_fails_bad_type
[07:05:15] [PASSED] pf_txn_reports_error
[07:05:15] [PASSED] pf_txn_sends_pf2guc
[07:05:15] [PASSED] pf_sends_pf2guc
[07:05:15] [SKIPPED] pf_loopback_nop
[07:05:15] [SKIPPED] pf_loopback_echo
[07:05:15] [SKIPPED] pf_loopback_fail
[07:05:15] [SKIPPED] pf_loopback_busy
[07:05:15] [SKIPPED] pf_loopback_retry
[07:05:15] ==================== [PASSED] pf_relay =====================
[07:05:15] ================== vf_relay (3 subtests) ===================
[07:05:15] [PASSED] vf_rejects_guc2vf_too_short
[07:05:15] [PASSED] vf_rejects_guc2vf_too_long
[07:05:15] [PASSED] vf_rejects_guc2vf_no_payload
[07:05:15] ==================== [PASSED] vf_relay =====================
[07:05:15] ================ pf_gt_config (9 subtests) =================
[07:05:15] [PASSED] fair_contexts_1vf
[07:05:15] [PASSED] fair_doorbells_1vf
[07:05:15] [PASSED] fair_ggtt_1vf
[07:05:15] ====================== fair_vram_1vf  ======================
[07:05:15] [PASSED] 3.50 GiB
[07:05:15] [PASSED] 11.5 GiB
[07:05:15] [PASSED] 15.5 GiB
[07:05:15] [PASSED] 31.5 GiB
[07:05:15] [PASSED] 63.5 GiB
[07:05:15] [PASSED] 1.91 GiB
[07:05:15] ================== [PASSED] fair_vram_1vf ==================
[07:05:15] ================ fair_vram_1vf_admin_only  =================
[07:05:15] [PASSED] 3.50 GiB
[07:05:15] [PASSED] 11.5 GiB
[07:05:15] [PASSED] 15.5 GiB
[07:05:15] [PASSED] 31.5 GiB
[07:05:15] [PASSED] 63.5 GiB
[07:05:15] [PASSED] 1.91 GiB
[07:05:15] ============ [PASSED] fair_vram_1vf_admin_only =============
[07:05:15] ====================== fair_contexts  ======================
[07:05:15] [PASSED] 1 VF
[07:05:15] [PASSED] 2 VFs
[07:05:15] [PASSED] 3 VFs
[07:05:15] [PASSED] 4 VFs
[07:05:15] [PASSED] 5 VFs
[07:05:15] [PASSED] 6 VFs
[07:05:15] [PASSED] 7 VFs
[07:05:15] [PASSED] 8 VFs
[07:05:15] [PASSED] 9 VFs
[07:05:15] [PASSED] 10 VFs
[07:05:15] [PASSED] 11 VFs
[07:05:15] [PASSED] 12 VFs
[07:05:15] [PASSED] 13 VFs
[07:05:15] [PASSED] 14 VFs
[07:05:15] [PASSED] 15 VFs
[07:05:15] [PASSED] 16 VFs
[07:05:15] [PASSED] 17 VFs
[07:05:15] [PASSED] 18 VFs
[07:05:15] [PASSED] 19 VFs
[07:05:15] [PASSED] 20 VFs
[07:05:15] [PASSED] 21 VFs
[07:05:15] [PASSED] 22 VFs
[07:05:15] [PASSED] 23 VFs
[07:05:15] [PASSED] 24 VFs
[07:05:15] [PASSED] 25 VFs
[07:05:15] [PASSED] 26 VFs
[07:05:15] [PASSED] 27 VFs
[07:05:15] [PASSED] 28 VFs
[07:05:15] [PASSED] 29 VFs
[07:05:15] [PASSED] 30 VFs
[07:05:15] [PASSED] 31 VFs
[07:05:15] [PASSED] 32 VFs
[07:05:15] [PASSED] 33 VFs
[07:05:15] [PASSED] 34 VFs
[07:05:15] [PASSED] 35 VFs
[07:05:15] [PASSED] 36 VFs
[07:05:15] [PASSED] 37 VFs
[07:05:15] [PASSED] 38 VFs
[07:05:15] [PASSED] 39 VFs
[07:05:15] [PASSED] 40 VFs
[07:05:15] [PASSED] 41 VFs
[07:05:15] [PASSED] 42 VFs
[07:05:15] [PASSED] 43 VFs
[07:05:15] [PASSED] 44 VFs
[07:05:15] [PASSED] 45 VFs
[07:05:15] [PASSED] 46 VFs
[07:05:15] [PASSED] 47 VFs
[07:05:15] [PASSED] 48 VFs
[07:05:15] [PASSED] 49 VFs
[07:05:15] [PASSED] 50 VFs
[07:05:15] [PASSED] 51 VFs
[07:05:15] [PASSED] 52 VFs
[07:05:15] [PASSED] 53 VFs
[07:05:15] [PASSED] 54 VFs
[07:05:15] [PASSED] 55 VFs
[07:05:15] [PASSED] 56 VFs
[07:05:15] [PASSED] 57 VFs
[07:05:15] [PASSED] 58 VFs
[07:05:15] [PASSED] 59 VFs
[07:05:15] [PASSED] 60 VFs
[07:05:15] [PASSED] 61 VFs
[07:05:15] [PASSED] 62 VFs
[07:05:15] [PASSED] 63 VFs
[07:05:15] ================== [PASSED] fair_contexts ==================
[07:05:15] ===================== fair_doorbells  ======================
[07:05:15] [PASSED] 1 VF
[07:05:15] [PASSED] 2 VFs
[07:05:15] [PASSED] 3 VFs
[07:05:15] [PASSED] 4 VFs
[07:05:15] [PASSED] 5 VFs
[07:05:15] [PASSED] 6 VFs
[07:05:15] [PASSED] 7 VFs
[07:05:15] [PASSED] 8 VFs
[07:05:15] [PASSED] 9 VFs
[07:05:15] [PASSED] 10 VFs
[07:05:15] [PASSED] 11 VFs
[07:05:15] [PASSED] 12 VFs
[07:05:15] [PASSED] 13 VFs
[07:05:15] [PASSED] 14 VFs
[07:05:15] [PASSED] 15 VFs
[07:05:15] [PASSED] 16 VFs
[07:05:15] [PASSED] 17 VFs
[07:05:15] [PASSED] 18 VFs
[07:05:15] [PASSED] 19 VFs
[07:05:15] [PASSED] 20 VFs
[07:05:15] [PASSED] 21 VFs
[07:05:15] [PASSED] 22 VFs
[07:05:15] [PASSED] 23 VFs
[07:05:15] [PASSED] 24 VFs
[07:05:15] [PASSED] 25 VFs
[07:05:15] [PASSED] 26 VFs
[07:05:15] [PASSED] 27 VFs
[07:05:15] [PASSED] 28 VFs
[07:05:15] [PASSED] 29 VFs
[07:05:15] [PASSED] 30 VFs
[07:05:15] [PASSED] 31 VFs
[07:05:15] [PASSED] 32 VFs
[07:05:15] [PASSED] 33 VFs
[07:05:15] [PASSED] 34 VFs
[07:05:15] [PASSED] 35 VFs
[07:05:15] [PASSED] 36 VFs
[07:05:15] [PASSED] 37 VFs
[07:05:15] [PASSED] 38 VFs
[07:05:15] [PASSED] 39 VFs
[07:05:15] [PASSED] 40 VFs
[07:05:15] [PASSED] 41 VFs
[07:05:15] [PASSED] 42 VFs
[07:05:15] [PASSED] 43 VFs
[07:05:15] [PASSED] 44 VFs
[07:05:15] [PASSED] 45 VFs
[07:05:15] [PASSED] 46 VFs
[07:05:15] [PASSED] 47 VFs
[07:05:15] [PASSED] 48 VFs
[07:05:15] [PASSED] 49 VFs
[07:05:15] [PASSED] 50 VFs
[07:05:15] [PASSED] 51 VFs
[07:05:15] [PASSED] 52 VFs
[07:05:15] [PASSED] 53 VFs
[07:05:15] [PASSED] 54 VFs
[07:05:15] [PASSED] 55 VFs
[07:05:15] [PASSED] 56 VFs
[07:05:15] [PASSED] 57 VFs
[07:05:15] [PASSED] 58 VFs
[07:05:15] [PASSED] 59 VFs
[07:05:15] [PASSED] 60 VFs
[07:05:15] [PASSED] 61 VFs
[07:05:15] [PASSED] 62 VFs
[07:05:15] [PASSED] 63 VFs
[07:05:15] ================= [PASSED] fair_doorbells ==================
[07:05:15] ======================== fair_ggtt  ========================
[07:05:15] [PASSED] 1 VF
[07:05:15] [PASSED] 2 VFs
[07:05:15] [PASSED] 3 VFs
[07:05:15] [PASSED] 4 VFs
[07:05:15] [PASSED] 5 VFs
[07:05:15] [PASSED] 6 VFs
[07:05:15] [PASSED] 7 VFs
[07:05:15] [PASSED] 8 VFs
[07:05:15] [PASSED] 9 VFs
[07:05:15] [PASSED] 10 VFs
[07:05:15] [PASSED] 11 VFs
[07:05:15] [PASSED] 12 VFs
[07:05:15] [PASSED] 13 VFs
[07:05:15] [PASSED] 14 VFs
[07:05:15] [PASSED] 15 VFs
[07:05:15] [PASSED] 16 VFs
[07:05:15] [PASSED] 17 VFs
[07:05:15] [PASSED] 18 VFs
[07:05:15] [PASSED] 19 VFs
[07:05:15] [PASSED] 20 VFs
[07:05:15] [PASSED] 21 VFs
[07:05:15] [PASSED] 22 VFs
[07:05:15] [PASSED] 23 VFs
[07:05:15] [PASSED] 24 VFs
[07:05:15] [PASSED] 25 VFs
[07:05:15] [PASSED] 26 VFs
[07:05:15] [PASSED] 27 VFs
[07:05:15] [PASSED] 28 VFs
[07:05:15] [PASSED] 29 VFs
[07:05:15] [PASSED] 30 VFs
[07:05:15] [PASSED] 31 VFs
[07:05:15] [PASSED] 32 VFs
[07:05:15] [PASSED] 33 VFs
[07:05:15] [PASSED] 34 VFs
[07:05:15] [PASSED] 35 VFs
[07:05:15] [PASSED] 36 VFs
[07:05:15] [PASSED] 37 VFs
[07:05:15] [PASSED] 38 VFs
[07:05:15] [PASSED] 39 VFs
[07:05:15] [PASSED] 40 VFs
[07:05:15] [PASSED] 41 VFs
[07:05:15] [PASSED] 42 VFs
[07:05:15] [PASSED] 43 VFs
[07:05:15] [PASSED] 44 VFs
[07:05:15] [PASSED] 45 VFs
[07:05:15] [PASSED] 46 VFs
[07:05:15] [PASSED] 47 VFs
[07:05:15] [PASSED] 48 VFs
[07:05:15] [PASSED] 49 VFs
[07:05:15] [PASSED] 50 VFs
[07:05:15] [PASSED] 51 VFs
[07:05:15] [PASSED] 52 VFs
[07:05:15] [PASSED] 53 VFs
[07:05:15] [PASSED] 54 VFs
[07:05:15] [PASSED] 55 VFs
[07:05:15] [PASSED] 56 VFs
[07:05:15] [PASSED] 57 VFs
[07:05:15] [PASSED] 58 VFs
[07:05:15] [PASSED] 59 VFs
[07:05:15] [PASSED] 60 VFs
[07:05:15] [PASSED] 61 VFs
[07:05:15] [PASSED] 62 VFs
[07:05:15] [PASSED] 63 VFs
[07:05:15] ==================== [PASSED] fair_ggtt ====================
[07:05:15] ======================== fair_vram  ========================
[07:05:15] [PASSED] 1 VF
[07:05:15] [PASSED] 2 VFs
[07:05:15] [PASSED] 3 VFs
[07:05:15] [PASSED] 4 VFs
[07:05:15] [PASSED] 5 VFs
[07:05:15] [PASSED] 6 VFs
[07:05:15] [PASSED] 7 VFs
[07:05:15] [PASSED] 8 VFs
[07:05:15] [PASSED] 9 VFs
[07:05:15] [PASSED] 10 VFs
[07:05:15] [PASSED] 11 VFs
[07:05:15] [PASSED] 12 VFs
[07:05:15] [PASSED] 13 VFs
[07:05:15] [PASSED] 14 VFs
[07:05:15] [PASSED] 15 VFs
[07:05:15] [PASSED] 16 VFs
[07:05:15] [PASSED] 17 VFs
[07:05:15] [PASSED] 18 VFs
[07:05:15] [PASSED] 19 VFs
[07:05:15] [PASSED] 20 VFs
[07:05:15] [PASSED] 21 VFs
[07:05:15] [PASSED] 22 VFs
[07:05:15] [PASSED] 23 VFs
[07:05:15] [PASSED] 24 VFs
[07:05:15] [PASSED] 25 VFs
[07:05:15] [PASSED] 26 VFs
[07:05:15] [PASSED] 27 VFs
[07:05:15] [PASSED] 28 VFs
[07:05:15] [PASSED] 29 VFs
[07:05:15] [PASSED] 30 VFs
[07:05:15] [PASSED] 31 VFs
[07:05:15] [PASSED] 32 VFs
[07:05:15] [PASSED] 33 VFs
[07:05:15] [PASSED] 34 VFs
[07:05:15] [PASSED] 35 VFs
[07:05:15] [PASSED] 36 VFs
[07:05:15] [PASSED] 37 VFs
[07:05:15] [PASSED] 38 VFs
[07:05:15] [PASSED] 39 VFs
[07:05:15] [PASSED] 40 VFs
[07:05:15] [PASSED] 41 VFs
[07:05:15] [PASSED] 42 VFs
[07:05:15] [PASSED] 43 VFs
[07:05:15] [PASSED] 44 VFs
[07:05:15] [PASSED] 45 VFs
[07:05:15] [PASSED] 46 VFs
[07:05:15] [PASSED] 47 VFs
[07:05:15] [PASSED] 48 VFs
[07:05:15] [PASSED] 49 VFs
[07:05:15] [PASSED] 50 VFs
[07:05:15] [PASSED] 51 VFs
[07:05:15] [PASSED] 52 VFs
[07:05:15] [PASSED] 53 VFs
[07:05:15] [PASSED] 54 VFs
[07:05:15] [PASSED] 55 VFs
[07:05:15] [PASSED] 56 VFs
[07:05:15] [PASSED] 57 VFs
[07:05:15] [PASSED] 58 VFs
[07:05:15] [PASSED] 59 VFs
[07:05:15] [PASSED] 60 VFs
[07:05:15] [PASSED] 61 VFs
[07:05:15] [PASSED] 62 VFs
[07:05:15] [PASSED] 63 VFs
[07:05:15] ==================== [PASSED] fair_vram ====================
[07:05:15] ================== [PASSED] pf_gt_config ===================
[07:05:15] ===================== lmtt (1 subtest) =====================
[07:05:15] ======================== test_ops  =========================
[07:05:15] [PASSED] 2-level
[07:05:15] [PASSED] multi-level
[07:05:15] ==================== [PASSED] test_ops =====================
[07:05:15] ====================== [PASSED] lmtt =======================
[07:05:15] ================= pf_service (11 subtests) =================
[07:05:15] [PASSED] pf_negotiate_any
[07:05:15] [PASSED] pf_negotiate_base_match
[07:05:15] [PASSED] pf_negotiate_base_newer
[07:05:15] [PASSED] pf_negotiate_base_next
[07:05:15] [SKIPPED] pf_negotiate_base_older
[07:05:15] [PASSED] pf_negotiate_base_prev
[07:05:15] [PASSED] pf_negotiate_latest_match
[07:05:15] [PASSED] pf_negotiate_latest_newer
[07:05:15] [PASSED] pf_negotiate_latest_next
[07:05:15] [SKIPPED] pf_negotiate_latest_older
[07:05:15] [SKIPPED] pf_negotiate_latest_prev
[07:05:15] =================== [PASSED] pf_service ====================
[07:05:15] ================= xe_guc_g2g (2 subtests) ==================
[07:05:15] ============== xe_live_guc_g2g_kunit_default  ==============
[07:05:15] ========= [SKIPPED] xe_live_guc_g2g_kunit_default ==========
[07:05:15] ============== xe_live_guc_g2g_kunit_allmem  ===============
[07:05:15] ========== [SKIPPED] xe_live_guc_g2g_kunit_allmem ==========
[07:05:15] =================== [SKIPPED] xe_guc_g2g ===================
[07:05:15] =================== xe_mocs (2 subtests) ===================
[07:05:15] ================ xe_live_mocs_kernel_kunit  ================
[07:05:15] =========== [SKIPPED] xe_live_mocs_kernel_kunit ============
[07:05:15] ================ xe_live_mocs_reset_kunit  =================
[07:05:15] ============ [SKIPPED] xe_live_mocs_reset_kunit ============
[07:05:15] ==================== [SKIPPED] xe_mocs =====================
[07:05:15] ================= xe_migrate (2 subtests) ==================
[07:05:15] ================= xe_migrate_sanity_kunit  =================
[07:05:15] ============ [SKIPPED] xe_migrate_sanity_kunit =============
[07:05:15] ================== xe_validate_ccs_kunit  ==================
[07:05:15] ============= [SKIPPED] xe_validate_ccs_kunit ==============
[07:05:15] =================== [SKIPPED] xe_migrate ===================
[07:05:15] ================== xe_dma_buf (1 subtest) ==================
[07:05:15] ==================== xe_dma_buf_kunit  =====================
[07:05:15] ================ [SKIPPED] xe_dma_buf_kunit ================
[07:05:15] =================== [SKIPPED] xe_dma_buf ===================
[07:05:15] ================= xe_bo_shrink (1 subtest) =================
[07:05:15] =================== xe_bo_shrink_kunit  ====================
[07:05:15] =============== [SKIPPED] xe_bo_shrink_kunit ===============
[07:05:15] ================== [SKIPPED] xe_bo_shrink ==================
[07:05:15] ==================== xe_bo (2 subtests) ====================
[07:05:15] ================== xe_ccs_migrate_kunit  ===================
[07:05:15] ============== [SKIPPED] xe_ccs_migrate_kunit ==============
[07:05:15] ==================== xe_bo_evict_kunit  ====================
[07:05:15] =============== [SKIPPED] xe_bo_evict_kunit ================
[07:05:15] ===================== [SKIPPED] xe_bo ======================
[07:05:15] ==================== args (13 subtests) ====================
[07:05:15] [PASSED] count_args_test
[07:05:15] [PASSED] call_args_example
[07:05:15] [PASSED] call_args_test
[07:05:15] [PASSED] drop_first_arg_example
[07:05:15] [PASSED] drop_first_arg_test
[07:05:15] [PASSED] first_arg_example
[07:05:15] [PASSED] first_arg_test
[07:05:15] [PASSED] last_arg_example
[07:05:15] [PASSED] last_arg_test
[07:05:15] [PASSED] pick_arg_example
[07:05:15] [PASSED] if_args_example
[07:05:15] [PASSED] if_args_test
[07:05:15] [PASSED] sep_comma_example
[07:05:15] ====================== [PASSED] args =======================
[07:05:15] =================== xe_pci (3 subtests) ====================
[07:05:15] ==================== check_graphics_ip  ====================
[07:05:15] [PASSED] 12.00 Xe_LP
[07:05:15] [PASSED] 12.10 Xe_LP+
[07:05:15] [PASSED] 12.55 Xe_HPG
[07:05:15] [PASSED] 12.60 Xe_HPC
[07:05:15] [PASSED] 12.70 Xe_LPG
[07:05:15] [PASSED] 12.71 Xe_LPG
[07:05:15] [PASSED] 12.74 Xe_LPG+
[07:05:15] [PASSED] 20.01 Xe2_HPG
[07:05:15] [PASSED] 20.02 Xe2_HPG
[07:05:15] [PASSED] 20.04 Xe2_LPG
[07:05:15] [PASSED] 30.00 Xe3_LPG
[07:05:15] [PASSED] 30.01 Xe3_LPG
[07:05:15] [PASSED] 30.03 Xe3_LPG
[07:05:15] [PASSED] 30.04 Xe3_LPG
[07:05:15] [PASSED] 30.05 Xe3_LPG
[07:05:15] [PASSED] 35.10 Xe3p_LPG
[07:05:15] [PASSED] 35.11 Xe3p_XPC
[07:05:15] ================ [PASSED] check_graphics_ip ================
[07:05:15] ===================== check_media_ip  ======================
[07:05:15] [PASSED] 12.00 Xe_M
[07:05:15] [PASSED] 12.55 Xe_HPM
[07:05:15] [PASSED] 13.00 Xe_LPM+
[07:05:15] [PASSED] 13.01 Xe2_HPM
[07:05:15] [PASSED] 20.00 Xe2_LPM
[07:05:15] [PASSED] 30.00 Xe3_LPM
[07:05:15] [PASSED] 30.02 Xe3_LPM
[07:05:15] [PASSED] 35.00 Xe3p_LPM
[07:05:15] [PASSED] 35.03 Xe3p_HPM
[07:05:15] ================= [PASSED] check_media_ip ==================
[07:05:15] =================== check_platform_desc  ===================
[07:05:15] [PASSED] 0x9A60 (TIGERLAKE)
[07:05:15] [PASSED] 0x9A68 (TIGERLAKE)
[07:05:15] [PASSED] 0x9A70 (TIGERLAKE)
[07:05:15] [PASSED] 0x9A40 (TIGERLAKE)
[07:05:15] [PASSED] 0x9A49 (TIGERLAKE)
[07:05:15] [PASSED] 0x9A59 (TIGERLAKE)
[07:05:15] [PASSED] 0x9A78 (TIGERLAKE)
[07:05:15] [PASSED] 0x9AC0 (TIGERLAKE)
[07:05:15] [PASSED] 0x9AC9 (TIGERLAKE)
[07:05:15] [PASSED] 0x9AD9 (TIGERLAKE)
[07:05:15] [PASSED] 0x9AF8 (TIGERLAKE)
[07:05:15] [PASSED] 0x4C80 (ROCKETLAKE)
[07:05:15] [PASSED] 0x4C8A (ROCKETLAKE)
[07:05:15] [PASSED] 0x4C8B (ROCKETLAKE)
[07:05:15] [PASSED] 0x4C8C (ROCKETLAKE)
[07:05:15] [PASSED] 0x4C90 (ROCKETLAKE)
[07:05:15] [PASSED] 0x4C9A (ROCKETLAKE)
[07:05:15] [PASSED] 0x4680 (ALDERLAKE_S)
[07:05:15] [PASSED] 0x4682 (ALDERLAKE_S)
[07:05:15] [PASSED] 0x4688 (ALDERLAKE_S)
[07:05:15] [PASSED] 0x468A (ALDERLAKE_S)
[07:05:15] [PASSED] 0x468B (ALDERLAKE_S)
[07:05:15] [PASSED] 0x4690 (ALDERLAKE_S)
[07:05:15] [PASSED] 0x4692 (ALDERLAKE_S)
[07:05:15] [PASSED] 0x4693 (ALDERLAKE_S)
[07:05:15] [PASSED] 0x46A0 (ALDERLAKE_P)
[07:05:15] [PASSED] 0x46A1 (ALDERLAKE_P)
[07:05:15] [PASSED] 0x46A2 (ALDERLAKE_P)
[07:05:15] [PASSED] 0x46A3 (ALDERLAKE_P)
[07:05:15] [PASSED] 0x46A6 (ALDERLAKE_P)
[07:05:15] [PASSED] 0x46A8 (ALDERLAKE_P)
[07:05:15] [PASSED] 0x46AA (ALDERLAKE_P)
[07:05:15] [PASSED] 0x462A (ALDERLAKE_P)
[07:05:15] [PASSED] 0x4626 (ALDERLAKE_P)
[07:05:15] [PASSED] 0x4628 (ALDERLAKE_P)
[07:05:15] [PASSED] 0x46B0 (ALDERLAKE_P)
[07:05:15] [PASSED] 0x46B1 (ALDERLAKE_P)
[07:05:15] [PASSED] 0x46B2 (ALDERLAKE_P)
[07:05:15] [PASSED] 0x46B3 (ALDERLAKE_P)
[07:05:15] [PASSED] 0x46C0 (ALDERLAKE_P)
[07:05:15] [PASSED] 0x46C1 (ALDERLAKE_P)
[07:05:15] [PASSED] 0x46C2 (ALDERLAKE_P)
[07:05:15] [PASSED] 0x46C3 (ALDERLAKE_P)
[07:05:15] [PASSED] 0x46D0 (ALDERLAKE_N)
[07:05:15] [PASSED] 0x46D1 (ALDERLAKE_N)
[07:05:15] [PASSED] 0x46D2 (ALDERLAKE_N)
[07:05:15] [PASSED] 0x46D3 (ALDERLAKE_N)
[07:05:15] [PASSED] 0x46D4 (ALDERLAKE_N)
[07:05:15] [PASSED] 0xA721 (ALDERLAKE_P)
[07:05:15] [PASSED] 0xA7A1 (ALDERLAKE_P)
[07:05:15] [PASSED] 0xA7A9 (ALDERLAKE_P)
[07:05:15] [PASSED] 0xA7AC (ALDERLAKE_P)
[07:05:15] [PASSED] 0xA7AD (ALDERLAKE_P)
[07:05:15] [PASSED] 0xA720 (ALDERLAKE_P)
[07:05:15] [PASSED] 0xA7A0 (ALDERLAKE_P)
[07:05:15] [PASSED] 0xA7A8 (ALDERLAKE_P)
[07:05:15] [PASSED] 0xA7AA (ALDERLAKE_P)
[07:05:15] [PASSED] 0xA7AB (ALDERLAKE_P)
[07:05:15] [PASSED] 0xA780 (ALDERLAKE_S)
[07:05:15] [PASSED] 0xA781 (ALDERLAKE_S)
[07:05:15] [PASSED] 0xA782 (ALDERLAKE_S)
[07:05:15] [PASSED] 0xA783 (ALDERLAKE_S)
[07:05:15] [PASSED] 0xA788 (ALDERLAKE_S)
[07:05:15] [PASSED] 0xA789 (ALDERLAKE_S)
[07:05:15] [PASSED] 0xA78A (ALDERLAKE_S)
[07:05:15] [PASSED] 0xA78B (ALDERLAKE_S)
[07:05:15] [PASSED] 0x4905 (DG1)
[07:05:15] [PASSED] 0x4906 (DG1)
[07:05:15] [PASSED] 0x4907 (DG1)
[07:05:15] [PASSED] 0x4908 (DG1)
[07:05:15] [PASSED] 0x4909 (DG1)
[07:05:15] [PASSED] 0x56C0 (DG2)
[07:05:15] [PASSED] 0x56C2 (DG2)
[07:05:15] [PASSED] 0x56C1 (DG2)
[07:05:15] [PASSED] 0x7D51 (METEORLAKE)
[07:05:15] [PASSED] 0x7DD1 (METEORLAKE)
[07:05:15] [PASSED] 0x7D41 (METEORLAKE)
[07:05:15] [PASSED] 0x7D67 (METEORLAKE)
[07:05:15] [PASSED] 0xB640 (METEORLAKE)
[07:05:15] [PASSED] 0x56A0 (DG2)
[07:05:15] [PASSED] 0x56A1 (DG2)
[07:05:15] [PASSED] 0x56A2 (DG2)
[07:05:15] [PASSED] 0x56BE (DG2)
[07:05:15] [PASSED] 0x56BF (DG2)
[07:05:15] [PASSED] 0x5690 (DG2)
[07:05:15] [PASSED] 0x5691 (DG2)
[07:05:15] [PASSED] 0x5692 (DG2)
[07:05:15] [PASSED] 0x56A5 (DG2)
[07:05:15] [PASSED] 0x56A6 (DG2)
[07:05:15] [PASSED] 0x56B0 (DG2)
[07:05:15] [PASSED] 0x56B1 (DG2)
[07:05:15] [PASSED] 0x56BA (DG2)
[07:05:15] [PASSED] 0x56BB (DG2)
[07:05:15] [PASSED] 0x56BC (DG2)
[07:05:15] [PASSED] 0x56BD (DG2)
[07:05:15] [PASSED] 0x5693 (DG2)
[07:05:15] [PASSED] 0x5694 (DG2)
[07:05:15] [PASSED] 0x5695 (DG2)
[07:05:15] [PASSED] 0x56A3 (DG2)
[07:05:15] [PASSED] 0x56A4 (DG2)
[07:05:15] [PASSED] 0x56B2 (DG2)
[07:05:15] [PASSED] 0x56B3 (DG2)
[07:05:15] [PASSED] 0x5696 (DG2)
[07:05:15] [PASSED] 0x5697 (DG2)
[07:05:15] [PASSED] 0xB69 (PVC)
[07:05:15] [PASSED] 0xB6E (PVC)
[07:05:15] [PASSED] 0xBD4 (PVC)
[07:05:15] [PASSED] 0xBD5 (PVC)
[07:05:15] [PASSED] 0xBD6 (PVC)
[07:05:15] [PASSED] 0xBD7 (PVC)
[07:05:15] [PASSED] 0xBD8 (PVC)
[07:05:15] [PASSED] 0xBD9 (PVC)
[07:05:15] [PASSED] 0xBDA (PVC)
[07:05:15] [PASSED] 0xBDB (PVC)
[07:05:15] [PASSED] 0xBE0 (PVC)
[07:05:15] [PASSED] 0xBE1 (PVC)
[07:05:15] [PASSED] 0xBE5 (PVC)
[07:05:15] [PASSED] 0x7D40 (METEORLAKE)
[07:05:15] [PASSED] 0x7D45 (METEORLAKE)
[07:05:15] [PASSED] 0x7D55 (METEORLAKE)
[07:05:15] [PASSED] 0x7D60 (METEORLAKE)
[07:05:15] [PASSED] 0x7DD5 (METEORLAKE)
[07:05:15] [PASSED] 0x6420 (LUNARLAKE)
[07:05:15] [PASSED] 0x64A0 (LUNARLAKE)
[07:05:15] [PASSED] 0x64B0 (LUNARLAKE)
[07:05:15] [PASSED] 0xE202 (BATTLEMAGE)
[07:05:15] [PASSED] 0xE209 (BATTLEMAGE)
[07:05:15] [PASSED] 0xE20B (BATTLEMAGE)
[07:05:15] [PASSED] 0xE20C (BATTLEMAGE)
[07:05:15] [PASSED] 0xE20D (BATTLEMAGE)
[07:05:15] [PASSED] 0xE210 (BATTLEMAGE)
[07:05:15] [PASSED] 0xE211 (BATTLEMAGE)
[07:05:15] [PASSED] 0xE212 (BATTLEMAGE)
[07:05:15] [PASSED] 0xE216 (BATTLEMAGE)
[07:05:15] [PASSED] 0xE220 (BATTLEMAGE)
[07:05:15] [PASSED] 0xE221 (BATTLEMAGE)
[07:05:15] [PASSED] 0xE222 (BATTLEMAGE)
[07:05:15] [PASSED] 0xE223 (BATTLEMAGE)
[07:05:15] [PASSED] 0xB080 (PANTHERLAKE)
[07:05:15] [PASSED] 0xB081 (PANTHERLAKE)
[07:05:15] [PASSED] 0xB082 (PANTHERLAKE)
[07:05:15] [PASSED] 0xB083 (PANTHERLAKE)
[07:05:15] [PASSED] 0xB084 (PANTHERLAKE)
[07:05:15] [PASSED] 0xB085 (PANTHERLAKE)
[07:05:15] [PASSED] 0xB086 (PANTHERLAKE)
[07:05:15] [PASSED] 0xB087 (PANTHERLAKE)
[07:05:15] [PASSED] 0xB08F (PANTHERLAKE)
[07:05:15] [PASSED] 0xB090 (PANTHERLAKE)
[07:05:15] [PASSED] 0xB0A0 (PANTHERLAKE)
[07:05:15] [PASSED] 0xB0B0 (PANTHERLAKE)
[07:05:15] [PASSED] 0xFD80 (PANTHERLAKE)
[07:05:15] [PASSED] 0xFD81 (PANTHERLAKE)
[07:05:15] [PASSED] 0xD740 (NOVALAKE_S)
[07:05:15] [PASSED] 0xD741 (NOVALAKE_S)
[07:05:15] [PASSED] 0xD742 (NOVALAKE_S)
[07:05:15] [PASSED] 0xD743 (NOVALAKE_S)
[07:05:15] [PASSED] 0xD744 (NOVALAKE_S)
[07:05:15] [PASSED] 0xD745 (NOVALAKE_S)
[07:05:15] [PASSED] 0x674C (CRESCENTISLAND)
[07:05:15] [PASSED] 0xD750 (NOVALAKE_P)
[07:05:15] [PASSED] 0xD751 (NOVALAKE_P)
[07:05:15] [PASSED] 0xD752 (NOVALAKE_P)
[07:05:15] [PASSED] 0xD753 (NOVALAKE_P)
[07:05:15] [PASSED] 0xD754 (NOVALAKE_P)
[07:05:15] [PASSED] 0xD755 (NOVALAKE_P)
[07:05:15] [PASSED] 0xD756 (NOVALAKE_P)
[07:05:15] [PASSED] 0xD757 (NOVALAKE_P)
[07:05:15] [PASSED] 0xD75F (NOVALAKE_P)
[07:05:15] =============== [PASSED] check_platform_desc ===============
[07:05:15] ===================== [PASSED] xe_pci ======================
[07:05:15] =================== xe_rtp (2 subtests) ====================
[07:05:15] =============== xe_rtp_process_to_sr_tests  ================
[07:05:15] [PASSED] coalesce-same-reg
[07:05:15] [PASSED] no-match-no-add
[07:05:15] [PASSED] match-or
[07:05:15] [PASSED] match-or-xfail
[07:05:15] [PASSED] no-match-no-add-multiple-rules
[07:05:15] [PASSED] two-regs-two-entries
[07:05:15] [PASSED] clr-one-set-other
[07:05:15] [PASSED] set-field
[07:05:15] [PASSED] conflict-duplicate
stty: 'standard input': Inappropriate ioctl for device
[07:05:15] [PASSED] conflict-not-disjoint
[07:05:15] [PASSED] conflict-reg-type
[07:05:15] =========== [PASSED] xe_rtp_process_to_sr_tests ============
[07:05:15] ================== xe_rtp_process_tests  ===================
[07:05:15] [PASSED] active1
[07:05:15] [PASSED] active2
[07:05:15] [PASSED] active-inactive
[07:05:15] [PASSED] inactive-active
[07:05:15] [PASSED] inactive-1st_or_active-inactive
[07:05:15] [PASSED] inactive-2nd_or_active-inactive
[07:05:15] [PASSED] inactive-last_or_active-inactive
[07:05:15] [PASSED] inactive-no_or_active-inactive
[07:05:15] ============== [PASSED] xe_rtp_process_tests ===============
[07:05:15] ===================== [PASSED] xe_rtp ======================
[07:05:15] ==================== xe_wa (1 subtest) =====================
[07:05:15] ======================== xe_wa_gt  =========================
[07:05:15] [PASSED] TIGERLAKE B0
[07:05:15] [PASSED] DG1 A0
[07:05:15] [PASSED] DG1 B0
[07:05:15] [PASSED] ALDERLAKE_S A0
[07:05:15] [PASSED] ALDERLAKE_S B0
[07:05:15] [PASSED] ALDERLAKE_S C0
[07:05:15] [PASSED] ALDERLAKE_S D0
[07:05:15] [PASSED] ALDERLAKE_P A0
[07:05:15] [PASSED] ALDERLAKE_P B0
[07:05:15] [PASSED] ALDERLAKE_P C0
[07:05:15] [PASSED] ALDERLAKE_S RPLS D0
[07:05:15] [PASSED] ALDERLAKE_P RPLU E0
[07:05:15] [PASSED] DG2 G10 C0
[07:05:15] [PASSED] DG2 G11 B1
[07:05:15] [PASSED] DG2 G12 A1
[07:05:15] [PASSED] METEORLAKE 12.70(Xe_LPG) A0 13.00(Xe_LPM+) A0
[07:05:15] [PASSED] METEORLAKE 12.71(Xe_LPG) A0 13.00(Xe_LPM+) A0
[07:05:15] [PASSED] METEORLAKE 12.74(Xe_LPG+) A0 13.00(Xe_LPM+) A0
[07:05:15] [PASSED] LUNARLAKE 20.04(Xe2_LPG) A0 20.00(Xe2_LPM) A0
[07:05:15] [PASSED] LUNARLAKE 20.04(Xe2_LPG) B0 20.00(Xe2_LPM) A0
[07:05:15] [PASSED] BATTLEMAGE 20.01(Xe2_HPG) A0 13.01(Xe2_HPM) A1
[07:05:15] [PASSED] PANTHERLAKE 30.00(Xe3_LPG) A0 30.00(Xe3_LPM) A0
[07:05:15] ==================== [PASSED] xe_wa_gt =====================
[07:05:15] ====================== [PASSED] xe_wa ======================
[07:05:15] ============================================================
[07:05:15] Testing complete. Ran 597 tests: passed: 579, skipped: 18
[07:05:15] Elapsed time: 35.754s total, 4.303s configuring, 30.834s building, 0.598s running

+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/tests/.kunitconfig
[07:05:15] Configuring KUnit Kernel ...
Regenerating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[07:05:17] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[07:05:41] Starting KUnit Kernel (1/1)...
[07:05:41] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[07:05:41] ============ drm_test_pick_cmdline (2 subtests) ============
[07:05:41] [PASSED] drm_test_pick_cmdline_res_1920_1080_60
[07:05:41] =============== drm_test_pick_cmdline_named  ===============
[07:05:41] [PASSED] NTSC
[07:05:41] [PASSED] NTSC-J
[07:05:41] [PASSED] PAL
[07:05:41] [PASSED] PAL-M
[07:05:41] =========== [PASSED] drm_test_pick_cmdline_named ===========
[07:05:41] ============== [PASSED] drm_test_pick_cmdline ==============
[07:05:41] == drm_test_atomic_get_connector_for_encoder (1 subtest) ===
[07:05:41] [PASSED] drm_test_drm_atomic_get_connector_for_encoder
[07:05:41] ==== [PASSED] drm_test_atomic_get_connector_for_encoder ====
[07:05:41] =========== drm_validate_clone_mode (2 subtests) ===========
[07:05:41] ============== drm_test_check_in_clone_mode  ===============
[07:05:41] [PASSED] in_clone_mode
[07:05:41] [PASSED] not_in_clone_mode
[07:05:41] ========== [PASSED] drm_test_check_in_clone_mode ===========
[07:05:41] =============== drm_test_check_valid_clones  ===============
[07:05:41] [PASSED] not_in_clone_mode
[07:05:41] [PASSED] valid_clone
[07:05:41] [PASSED] invalid_clone
[07:05:41] =========== [PASSED] drm_test_check_valid_clones ===========
[07:05:41] ============= [PASSED] drm_validate_clone_mode =============
[07:05:41] ============= drm_validate_modeset (1 subtest) =============
[07:05:41] [PASSED] drm_test_check_connector_changed_modeset
[07:05:41] ============== [PASSED] drm_validate_modeset ===============
[07:05:41] ====== drm_test_bridge_get_current_state (2 subtests) ======
[07:05:41] [PASSED] drm_test_drm_bridge_get_current_state_atomic
[07:05:41] [PASSED] drm_test_drm_bridge_get_current_state_legacy
[07:05:41] ======== [PASSED] drm_test_bridge_get_current_state ========
[07:05:41] ====== drm_test_bridge_helper_reset_crtc (3 subtests) ======
[07:05:41] [PASSED] drm_test_drm_bridge_helper_reset_crtc_atomic
[07:05:41] [PASSED] drm_test_drm_bridge_helper_reset_crtc_atomic_disabled
[07:05:41] [PASSED] drm_test_drm_bridge_helper_reset_crtc_legacy
[07:05:41] ======== [PASSED] drm_test_bridge_helper_reset_crtc ========
[07:05:41] ============== drm_bridge_alloc (2 subtests) ===============
[07:05:41] [PASSED] drm_test_drm_bridge_alloc_basic
[07:05:41] [PASSED] drm_test_drm_bridge_alloc_get_put
[07:05:41] ================ [PASSED] drm_bridge_alloc =================
[07:05:41] ============= drm_cmdline_parser (40 subtests) =============
[07:05:41] [PASSED] drm_test_cmdline_force_d_only
[07:05:41] [PASSED] drm_test_cmdline_force_D_only_dvi
[07:05:41] [PASSED] drm_test_cmdline_force_D_only_hdmi
[07:05:41] [PASSED] drm_test_cmdline_force_D_only_not_digital
[07:05:41] [PASSED] drm_test_cmdline_force_e_only
[07:05:41] [PASSED] drm_test_cmdline_res
[07:05:41] [PASSED] drm_test_cmdline_res_vesa
[07:05:41] [PASSED] drm_test_cmdline_res_vesa_rblank
[07:05:41] [PASSED] drm_test_cmdline_res_rblank
[07:05:41] [PASSED] drm_test_cmdline_res_bpp
[07:05:41] [PASSED] drm_test_cmdline_res_refresh
[07:05:41] [PASSED] drm_test_cmdline_res_bpp_refresh
[07:05:41] [PASSED] drm_test_cmdline_res_bpp_refresh_interlaced
[07:05:41] [PASSED] drm_test_cmdline_res_bpp_refresh_margins
[07:05:41] [PASSED] drm_test_cmdline_res_bpp_refresh_force_off
[07:05:41] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on
[07:05:41] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on_analog
[07:05:41] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on_digital
[07:05:41] [PASSED] drm_test_cmdline_res_bpp_refresh_interlaced_margins_force_on
[07:05:41] [PASSED] drm_test_cmdline_res_margins_force_on
[07:05:41] [PASSED] drm_test_cmdline_res_vesa_margins
[07:05:41] [PASSED] drm_test_cmdline_name
[07:05:41] [PASSED] drm_test_cmdline_name_bpp
[07:05:41] [PASSED] drm_test_cmdline_name_option
[07:05:41] [PASSED] drm_test_cmdline_name_bpp_option
[07:05:41] [PASSED] drm_test_cmdline_rotate_0
[07:05:41] [PASSED] drm_test_cmdline_rotate_90
[07:05:41] [PASSED] drm_test_cmdline_rotate_180
[07:05:41] [PASSED] drm_test_cmdline_rotate_270
[07:05:41] [PASSED] drm_test_cmdline_hmirror
[07:05:41] [PASSED] drm_test_cmdline_vmirror
[07:05:41] [PASSED] drm_test_cmdline_margin_options
[07:05:41] [PASSED] drm_test_cmdline_multiple_options
[07:05:41] [PASSED] drm_test_cmdline_bpp_extra_and_option
[07:05:41] [PASSED] drm_test_cmdline_extra_and_option
[07:05:41] [PASSED] drm_test_cmdline_freestanding_options
[07:05:41] [PASSED] drm_test_cmdline_freestanding_force_e_and_options
[07:05:41] [PASSED] drm_test_cmdline_panel_orientation
[07:05:41] ================ drm_test_cmdline_invalid  =================
[07:05:41] [PASSED] margin_only
[07:05:41] [PASSED] interlace_only
[07:05:41] [PASSED] res_missing_x
[07:05:41] [PASSED] res_missing_y
[07:05:41] [PASSED] res_bad_y
[07:05:41] [PASSED] res_missing_y_bpp
[07:05:41] [PASSED] res_bad_bpp
[07:05:41] [PASSED] res_bad_refresh
[07:05:41] [PASSED] res_bpp_refresh_force_on_off
[07:05:41] [PASSED] res_invalid_mode
[07:05:41] [PASSED] res_bpp_wrong_place_mode
[07:05:41] [PASSED] name_bpp_refresh
[07:05:41] [PASSED] name_refresh
[07:05:41] [PASSED] name_refresh_wrong_mode
[07:05:41] [PASSED] name_refresh_invalid_mode
[07:05:41] [PASSED] rotate_multiple
[07:05:41] [PASSED] rotate_invalid_val
[07:05:41] [PASSED] rotate_truncated
[07:05:41] [PASSED] invalid_option
[07:05:41] [PASSED] invalid_tv_option
[07:05:41] [PASSED] truncated_tv_option
[07:05:41] ============ [PASSED] drm_test_cmdline_invalid =============
[07:05:41] =============== drm_test_cmdline_tv_options  ===============
[07:05:41] [PASSED] NTSC
[07:05:41] [PASSED] NTSC_443
[07:05:41] [PASSED] NTSC_J
[07:05:41] [PASSED] PAL
[07:05:41] [PASSED] PAL_M
[07:05:41] [PASSED] PAL_N
[07:05:41] [PASSED] SECAM
[07:05:41] [PASSED] MONO_525
[07:05:41] [PASSED] MONO_625
[07:05:41] =========== [PASSED] drm_test_cmdline_tv_options ===========
[07:05:41] =============== [PASSED] drm_cmdline_parser ================
[07:05:41] ========== drmm_connector_hdmi_init (20 subtests) ==========
[07:05:41] [PASSED] drm_test_connector_hdmi_init_valid
[07:05:41] [PASSED] drm_test_connector_hdmi_init_bpc_8
[07:05:41] [PASSED] drm_test_connector_hdmi_init_bpc_10
[07:05:41] [PASSED] drm_test_connector_hdmi_init_bpc_12
[07:05:41] [PASSED] drm_test_connector_hdmi_init_bpc_invalid
[07:05:41] [PASSED] drm_test_connector_hdmi_init_bpc_null
[07:05:41] [PASSED] drm_test_connector_hdmi_init_formats_empty
[07:05:41] [PASSED] drm_test_connector_hdmi_init_formats_no_rgb
[07:05:41] === drm_test_connector_hdmi_init_formats_yuv420_allowed  ===
[07:05:41] [PASSED] supported_formats=0x9 yuv420_allowed=1
[07:05:41] [PASSED] supported_formats=0x9 yuv420_allowed=0
[07:05:41] [PASSED] supported_formats=0x5 yuv420_allowed=1
[07:05:41] [PASSED] supported_formats=0x5 yuv420_allowed=0
[07:05:41] === [PASSED] drm_test_connector_hdmi_init_formats_yuv420_allowed ===
[07:05:41] [PASSED] drm_test_connector_hdmi_init_null_ddc
[07:05:41] [PASSED] drm_test_connector_hdmi_init_null_product
[07:05:41] [PASSED] drm_test_connector_hdmi_init_null_vendor
[07:05:41] [PASSED] drm_test_connector_hdmi_init_product_length_exact
[07:05:41] [PASSED] drm_test_connector_hdmi_init_product_length_too_long
[07:05:41] [PASSED] drm_test_connector_hdmi_init_product_valid
[07:05:41] [PASSED] drm_test_connector_hdmi_init_vendor_length_exact
[07:05:41] [PASSED] drm_test_connector_hdmi_init_vendor_length_too_long
[07:05:41] [PASSED] drm_test_connector_hdmi_init_vendor_valid
[07:05:41] ========= drm_test_connector_hdmi_init_type_valid  =========
[07:05:41] [PASSED] HDMI-A
[07:05:41] [PASSED] HDMI-B
[07:05:41] ===== [PASSED] drm_test_connector_hdmi_init_type_valid =====
[07:05:41] ======== drm_test_connector_hdmi_init_type_invalid  ========
[07:05:41] [PASSED] Unknown
[07:05:41] [PASSED] VGA
[07:05:41] [PASSED] DVI-I
[07:05:41] [PASSED] DVI-D
[07:05:41] [PASSED] DVI-A
[07:05:41] [PASSED] Composite
[07:05:41] [PASSED] SVIDEO
[07:05:41] [PASSED] LVDS
[07:05:41] [PASSED] Component
[07:05:41] [PASSED] DIN
[07:05:41] [PASSED] DP
[07:05:41] [PASSED] TV
[07:05:41] [PASSED] eDP
[07:05:41] [PASSED] Virtual
[07:05:41] [PASSED] DSI
[07:05:41] [PASSED] DPI
[07:05:41] [PASSED] Writeback
[07:05:41] [PASSED] SPI
[07:05:41] [PASSED] USB
[07:05:41] ==== [PASSED] drm_test_connector_hdmi_init_type_invalid ====
[07:05:41] ============ [PASSED] drmm_connector_hdmi_init =============
[07:05:41] ============= drmm_connector_init (3 subtests) =============
[07:05:41] [PASSED] drm_test_drmm_connector_init
[07:05:41] [PASSED] drm_test_drmm_connector_init_null_ddc
[07:05:41] ========= drm_test_drmm_connector_init_type_valid  =========
[07:05:41] [PASSED] Unknown
[07:05:41] [PASSED] VGA
[07:05:41] [PASSED] DVI-I
[07:05:41] [PASSED] DVI-D
[07:05:41] [PASSED] DVI-A
[07:05:41] [PASSED] Composite
[07:05:41] [PASSED] SVIDEO
[07:05:41] [PASSED] LVDS
[07:05:41] [PASSED] Component
[07:05:41] [PASSED] DIN
[07:05:41] [PASSED] DP
[07:05:41] [PASSED] HDMI-A
[07:05:41] [PASSED] HDMI-B
[07:05:41] [PASSED] TV
[07:05:41] [PASSED] eDP
[07:05:41] [PASSED] Virtual
[07:05:41] [PASSED] DSI
[07:05:41] [PASSED] DPI
[07:05:41] [PASSED] Writeback
[07:05:41] [PASSED] SPI
[07:05:41] [PASSED] USB
[07:05:41] ===== [PASSED] drm_test_drmm_connector_init_type_valid =====
[07:05:41] =============== [PASSED] drmm_connector_init ===============
[07:05:41] ========= drm_connector_dynamic_init (6 subtests) ==========
[07:05:41] [PASSED] drm_test_drm_connector_dynamic_init
[07:05:41] [PASSED] drm_test_drm_connector_dynamic_init_null_ddc
[07:05:41] [PASSED] drm_test_drm_connector_dynamic_init_not_added
[07:05:41] [PASSED] drm_test_drm_connector_dynamic_init_properties
[07:05:41] ===== drm_test_drm_connector_dynamic_init_type_valid  ======
[07:05:41] [PASSED] Unknown
[07:05:41] [PASSED] VGA
[07:05:41] [PASSED] DVI-I
[07:05:41] [PASSED] DVI-D
[07:05:41] [PASSED] DVI-A
[07:05:41] [PASSED] Composite
[07:05:41] [PASSED] SVIDEO
[07:05:41] [PASSED] LVDS
[07:05:41] [PASSED] Component
[07:05:41] [PASSED] DIN
[07:05:41] [PASSED] DP
[07:05:41] [PASSED] HDMI-A
[07:05:41] [PASSED] HDMI-B
[07:05:41] [PASSED] TV
[07:05:41] [PASSED] eDP
[07:05:41] [PASSED] Virtual
[07:05:41] [PASSED] DSI
[07:05:41] [PASSED] DPI
[07:05:41] [PASSED] Writeback
[07:05:41] [PASSED] SPI
[07:05:41] [PASSED] USB
[07:05:41] = [PASSED] drm_test_drm_connector_dynamic_init_type_valid ==
[07:05:41] ======== drm_test_drm_connector_dynamic_init_name  =========
[07:05:41] [PASSED] Unknown
[07:05:41] [PASSED] VGA
[07:05:41] [PASSED] DVI-I
[07:05:41] [PASSED] DVI-D
[07:05:41] [PASSED] DVI-A
[07:05:41] [PASSED] Composite
[07:05:41] [PASSED] SVIDEO
[07:05:41] [PASSED] LVDS
[07:05:41] [PASSED] Component
[07:05:41] [PASSED] DIN
[07:05:41] [PASSED] DP
[07:05:41] [PASSED] HDMI-A
[07:05:41] [PASSED] HDMI-B
[07:05:41] [PASSED] TV
[07:05:41] [PASSED] eDP
[07:05:41] [PASSED] Virtual
[07:05:41] [PASSED] DSI
[07:05:41] [PASSED] DPI
[07:05:41] [PASSED] Writeback
[07:05:41] [PASSED] SPI
[07:05:41] [PASSED] USB
[07:05:41] ==== [PASSED] drm_test_drm_connector_dynamic_init_name =====
[07:05:41] =========== [PASSED] drm_connector_dynamic_init ============
[07:05:41] ==== drm_connector_dynamic_register_early (4 subtests) =====
[07:05:41] [PASSED] drm_test_drm_connector_dynamic_register_early_on_list
[07:05:41] [PASSED] drm_test_drm_connector_dynamic_register_early_defer
[07:05:41] [PASSED] drm_test_drm_connector_dynamic_register_early_no_init
[07:05:41] [PASSED] drm_test_drm_connector_dynamic_register_early_no_mode_object
[07:05:41] ====== [PASSED] drm_connector_dynamic_register_early =======
[07:05:41] ======= drm_connector_dynamic_register (7 subtests) ========
[07:05:41] [PASSED] drm_test_drm_connector_dynamic_register_on_list
[07:05:41] [PASSED] drm_test_drm_connector_dynamic_register_no_defer
[07:05:41] [PASSED] drm_test_drm_connector_dynamic_register_no_init
[07:05:41] [PASSED] drm_test_drm_connector_dynamic_register_mode_object
[07:05:41] [PASSED] drm_test_drm_connector_dynamic_register_sysfs
[07:05:41] [PASSED] drm_test_drm_connector_dynamic_register_sysfs_name
[07:05:41] [PASSED] drm_test_drm_connector_dynamic_register_debugfs
[07:05:41] ========= [PASSED] drm_connector_dynamic_register ==========
[07:05:41] = drm_connector_attach_broadcast_rgb_property (2 subtests) =
[07:05:41] [PASSED] drm_test_drm_connector_attach_broadcast_rgb_property
[07:05:41] [PASSED] drm_test_drm_connector_attach_broadcast_rgb_property_hdmi_connector
[07:05:41] === [PASSED] drm_connector_attach_broadcast_rgb_property ===
[07:05:41] ========== drm_get_tv_mode_from_name (2 subtests) ==========
[07:05:41] ========== drm_test_get_tv_mode_from_name_valid  ===========
[07:05:41] [PASSED] NTSC
[07:05:41] [PASSED] NTSC-443
[07:05:41] [PASSED] NTSC-J
[07:05:41] [PASSED] PAL
[07:05:41] [PASSED] PAL-M
[07:05:41] [PASSED] PAL-N
[07:05:41] [PASSED] SECAM
[07:05:41] [PASSED] Mono
[07:05:41] ====== [PASSED] drm_test_get_tv_mode_from_name_valid =======
[07:05:41] [PASSED] drm_test_get_tv_mode_from_name_truncated
[07:05:41] ============ [PASSED] drm_get_tv_mode_from_name ============
[07:05:41] = drm_test_connector_hdmi_compute_mode_clock (12 subtests) =
[07:05:41] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb
[07:05:41] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_10bpc
[07:05:41] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_10bpc_vic_1
[07:05:41] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_12bpc
[07:05:41] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_12bpc_vic_1
[07:05:41] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_double
[07:05:41] = drm_test_connector_hdmi_compute_mode_clock_yuv420_valid  =
[07:05:41] [PASSED] VIC 96
[07:05:41] [PASSED] VIC 97
[07:05:41] [PASSED] VIC 101
[07:05:41] [PASSED] VIC 102
[07:05:41] [PASSED] VIC 106
[07:05:41] [PASSED] VIC 107
[07:05:41] === [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_valid ===
[07:05:41] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_10_bpc
[07:05:41] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_12_bpc
[07:05:41] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_8_bpc
[07:05:41] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_10_bpc
[07:05:41] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_12_bpc
[07:05:41] === [PASSED] drm_test_connector_hdmi_compute_mode_clock ====
[07:05:41] == drm_hdmi_connector_get_broadcast_rgb_name (2 subtests) ==
[07:05:41] === drm_test_drm_hdmi_connector_get_broadcast_rgb_name  ====
[07:05:41] [PASSED] Automatic
[07:05:41] [PASSED] Full
[07:05:41] [PASSED] Limited 16:235
[07:05:41] === [PASSED] drm_test_drm_hdmi_connector_get_broadcast_rgb_name ===
[07:05:41] [PASSED] drm_test_drm_hdmi_connector_get_broadcast_rgb_name_invalid
[07:05:41] ==== [PASSED] drm_hdmi_connector_get_broadcast_rgb_name ====
[07:05:41] == drm_hdmi_connector_get_output_format_name (2 subtests) ==
[07:05:41] === drm_test_drm_hdmi_connector_get_output_format_name  ====
[07:05:41] [PASSED] RGB
[07:05:41] [PASSED] YUV 4:2:0
[07:05:41] [PASSED] YUV 4:2:2
[07:05:41] [PASSED] YUV 4:4:4
[07:05:41] === [PASSED] drm_test_drm_hdmi_connector_get_output_format_name ===
[07:05:41] [PASSED] drm_test_drm_hdmi_connector_get_output_format_name_invalid
[07:05:41] ==== [PASSED] drm_hdmi_connector_get_output_format_name ====
[07:05:41] ============= drm_damage_helper (21 subtests) ==============
[07:05:41] [PASSED] drm_test_damage_iter_no_damage
[07:05:41] [PASSED] drm_test_damage_iter_no_damage_fractional_src
[07:05:41] [PASSED] drm_test_damage_iter_no_damage_src_moved
[07:05:41] [PASSED] drm_test_damage_iter_no_damage_fractional_src_moved
[07:05:41] [PASSED] drm_test_damage_iter_no_damage_not_visible
[07:05:41] [PASSED] drm_test_damage_iter_no_damage_no_crtc
[07:05:41] [PASSED] drm_test_damage_iter_no_damage_no_fb
[07:05:41] [PASSED] drm_test_damage_iter_simple_damage
[07:05:41] [PASSED] drm_test_damage_iter_single_damage
[07:05:41] [PASSED] drm_test_damage_iter_single_damage_intersect_src
[07:05:41] [PASSED] drm_test_damage_iter_single_damage_outside_src
[07:05:41] [PASSED] drm_test_damage_iter_single_damage_fractional_src
[07:05:41] [PASSED] drm_test_damage_iter_single_damage_intersect_fractional_src
[07:05:41] [PASSED] drm_test_damage_iter_single_damage_outside_fractional_src
[07:05:41] [PASSED] drm_test_damage_iter_single_damage_src_moved
[07:05:41] [PASSED] drm_test_damage_iter_single_damage_fractional_src_moved
[07:05:41] [PASSED] drm_test_damage_iter_damage
[07:05:41] [PASSED] drm_test_damage_iter_damage_one_intersect
[07:05:41] [PASSED] drm_test_damage_iter_damage_one_outside
[07:05:41] [PASSED] drm_test_damage_iter_damage_src_moved
[07:05:41] [PASSED] drm_test_damage_iter_damage_not_visible
[07:05:41] ================ [PASSED] drm_damage_helper ================
[07:05:41] ============== drm_dp_mst_helper (3 subtests) ==============
[07:05:41] ============== drm_test_dp_mst_calc_pbn_mode  ==============
[07:05:41] [PASSED] Clock 154000 BPP 30 DSC disabled
[07:05:41] [PASSED] Clock 234000 BPP 30 DSC disabled
[07:05:41] [PASSED] Clock 297000 BPP 24 DSC disabled
[07:05:41] [PASSED] Clock 332880 BPP 24 DSC enabled
[07:05:41] [PASSED] Clock 324540 BPP 24 DSC enabled
[07:05:41] ========== [PASSED] drm_test_dp_mst_calc_pbn_mode ==========
[07:05:41] ============== drm_test_dp_mst_calc_pbn_div  ===============
[07:05:41] [PASSED] Link rate 2000000 lane count 4
[07:05:41] [PASSED] Link rate 2000000 lane count 2
[07:05:41] [PASSED] Link rate 2000000 lane count 1
[07:05:41] [PASSED] Link rate 1350000 lane count 4
[07:05:41] [PASSED] Link rate 1350000 lane count 2
[07:05:41] [PASSED] Link rate 1350000 lane count 1
[07:05:41] [PASSED] Link rate 1000000 lane count 4
[07:05:41] [PASSED] Link rate 1000000 lane count 2
[07:05:41] [PASSED] Link rate 1000000 lane count 1
[07:05:41] [PASSED] Link rate 810000 lane count 4
[07:05:41] [PASSED] Link rate 810000 lane count 2
[07:05:41] [PASSED] Link rate 810000 lane count 1
[07:05:41] [PASSED] Link rate 540000 lane count 4
[07:05:41] [PASSED] Link rate 540000 lane count 2
[07:05:41] [PASSED] Link rate 540000 lane count 1
[07:05:41] [PASSED] Link rate 270000 lane count 4
[07:05:41] [PASSED] Link rate 270000 lane count 2
[07:05:41] [PASSED] Link rate 270000 lane count 1
[07:05:41] [PASSED] Link rate 162000 lane count 4
[07:05:41] [PASSED] Link rate 162000 lane count 2
[07:05:41] [PASSED] Link rate 162000 lane count 1
[07:05:41] ========== [PASSED] drm_test_dp_mst_calc_pbn_div ===========
[07:05:41] ========= drm_test_dp_mst_sideband_msg_req_decode  =========
[07:05:41] [PASSED] DP_ENUM_PATH_RESOURCES with port number
[07:05:41] [PASSED] DP_POWER_UP_PHY with port number
[07:05:41] [PASSED] DP_POWER_DOWN_PHY with port number
[07:05:41] [PASSED] DP_ALLOCATE_PAYLOAD with SDP stream sinks
[07:05:41] [PASSED] DP_ALLOCATE_PAYLOAD with port number
[07:05:41] [PASSED] DP_ALLOCATE_PAYLOAD with VCPI
[07:05:41] [PASSED] DP_ALLOCATE_PAYLOAD with PBN
[07:05:41] [PASSED] DP_QUERY_PAYLOAD with port number
[07:05:41] [PASSED] DP_QUERY_PAYLOAD with VCPI
[07:05:41] [PASSED] DP_REMOTE_DPCD_READ with port number
[07:05:41] [PASSED] DP_REMOTE_DPCD_READ with DPCD address
[07:05:41] [PASSED] DP_REMOTE_DPCD_READ with max number of bytes
[07:05:41] [PASSED] DP_REMOTE_DPCD_WRITE with port number
[07:05:41] [PASSED] DP_REMOTE_DPCD_WRITE with DPCD address
[07:05:41] [PASSED] DP_REMOTE_DPCD_WRITE with data array
[07:05:41] [PASSED] DP_REMOTE_I2C_READ with port number
[07:05:41] [PASSED] DP_REMOTE_I2C_READ with I2C device ID
[07:05:41] [PASSED] DP_REMOTE_I2C_READ with transactions array
[07:05:41] [PASSED] DP_REMOTE_I2C_WRITE with port number
[07:05:41] [PASSED] DP_REMOTE_I2C_WRITE with I2C device ID
[07:05:41] [PASSED] DP_REMOTE_I2C_WRITE with data array
[07:05:41] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream ID
[07:05:41] [PASSED] DP_QUERY_STREAM_ENC_STATUS with client ID
[07:05:41] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream event
[07:05:41] [PASSED] DP_QUERY_STREAM_ENC_STATUS with valid stream event
[07:05:41] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream behavior
[07:05:41] [PASSED] DP_QUERY_STREAM_ENC_STATUS with a valid stream behavior
[07:05:41] ===== [PASSED] drm_test_dp_mst_sideband_msg_req_decode =====
[07:05:41] ================ [PASSED] drm_dp_mst_helper ================
[07:05:41] ================== drm_exec (7 subtests) ===================
[07:05:41] [PASSED] sanitycheck
[07:05:41] [PASSED] test_lock
[07:05:41] [PASSED] test_lock_unlock
[07:05:41] [PASSED] test_duplicates
[07:05:41] [PASSED] test_prepare
[07:05:41] [PASSED] test_prepare_array
[07:05:41] [PASSED] test_multiple_loops
[07:05:41] ==================== [PASSED] drm_exec =====================
[07:05:41] =========== drm_format_helper_test (17 subtests) ===========
[07:05:41] ============== drm_test_fb_xrgb8888_to_gray8  ==============
[07:05:41] [PASSED] single_pixel_source_buffer
[07:05:41] [PASSED] single_pixel_clip_rectangle
[07:05:41] [PASSED] well_known_colors
[07:05:41] [PASSED] destination_pitch
[07:05:41] ========== [PASSED] drm_test_fb_xrgb8888_to_gray8 ==========
[07:05:41] ============= drm_test_fb_xrgb8888_to_rgb332  ==============
[07:05:41] [PASSED] single_pixel_source_buffer
[07:05:41] [PASSED] single_pixel_clip_rectangle
[07:05:41] [PASSED] well_known_colors
[07:05:41] [PASSED] destination_pitch
[07:05:41] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb332 ==========
[07:05:41] ============= drm_test_fb_xrgb8888_to_rgb565  ==============
[07:05:41] [PASSED] single_pixel_source_buffer
[07:05:41] [PASSED] single_pixel_clip_rectangle
[07:05:41] [PASSED] well_known_colors
[07:05:41] [PASSED] destination_pitch
[07:05:41] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb565 ==========
[07:05:41] ============ drm_test_fb_xrgb8888_to_xrgb1555  =============
[07:05:41] [PASSED] single_pixel_source_buffer
[07:05:41] [PASSED] single_pixel_clip_rectangle
[07:05:41] [PASSED] well_known_colors
[07:05:41] [PASSED] destination_pitch
[07:05:41] ======== [PASSED] drm_test_fb_xrgb8888_to_xrgb1555 =========
[07:05:41] ============ drm_test_fb_xrgb8888_to_argb1555  =============
[07:05:41] [PASSED] single_pixel_source_buffer
[07:05:41] [PASSED] single_pixel_clip_rectangle
[07:05:41] [PASSED] well_known_colors
[07:05:41] [PASSED] destination_pitch
[07:05:41] ======== [PASSED] drm_test_fb_xrgb8888_to_argb1555 =========
[07:05:41] ============ drm_test_fb_xrgb8888_to_rgba5551  =============
[07:05:41] [PASSED] single_pixel_source_buffer
[07:05:41] [PASSED] single_pixel_clip_rectangle
[07:05:41] [PASSED] well_known_colors
[07:05:41] [PASSED] destination_pitch
[07:05:41] ======== [PASSED] drm_test_fb_xrgb8888_to_rgba5551 =========
[07:05:41] ============= drm_test_fb_xrgb8888_to_rgb888  ==============
[07:05:41] [PASSED] single_pixel_source_buffer
[07:05:41] [PASSED] single_pixel_clip_rectangle
[07:05:41] [PASSED] well_known_colors
[07:05:41] [PASSED] destination_pitch
[07:05:41] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb888 ==========
[07:05:41] ============= drm_test_fb_xrgb8888_to_bgr888  ==============
[07:05:41] [PASSED] single_pixel_source_buffer
[07:05:41] [PASSED] single_pixel_clip_rectangle
[07:05:41] [PASSED] well_known_colors
[07:05:41] [PASSED] destination_pitch
[07:05:41] ========= [PASSED] drm_test_fb_xrgb8888_to_bgr888 ==========
[07:05:41] ============ drm_test_fb_xrgb8888_to_argb8888  =============
[07:05:41] [PASSED] single_pixel_source_buffer
[07:05:41] [PASSED] single_pixel_clip_rectangle
[07:05:41] [PASSED] well_known_colors
[07:05:41] [PASSED] destination_pitch
[07:05:41] ======== [PASSED] drm_test_fb_xrgb8888_to_argb8888 =========
[07:05:41] =========== drm_test_fb_xrgb8888_to_xrgb2101010  ===========
[07:05:41] [PASSED] single_pixel_source_buffer
[07:05:41] [PASSED] single_pixel_clip_rectangle
[07:05:41] [PASSED] well_known_colors
[07:05:41] [PASSED] destination_pitch
[07:05:41] ======= [PASSED] drm_test_fb_xrgb8888_to_xrgb2101010 =======
[07:05:41] =========== drm_test_fb_xrgb8888_to_argb2101010  ===========
[07:05:41] [PASSED] single_pixel_source_buffer
[07:05:41] [PASSED] single_pixel_clip_rectangle
[07:05:41] [PASSED] well_known_colors
[07:05:41] [PASSED] destination_pitch
[07:05:41] ======= [PASSED] drm_test_fb_xrgb8888_to_argb2101010 =======
[07:05:41] ============== drm_test_fb_xrgb8888_to_mono  ===============
[07:05:41] [PASSED] single_pixel_source_buffer
[07:05:41] [PASSED] single_pixel_clip_rectangle
[07:05:41] [PASSED] well_known_colors
[07:05:41] [PASSED] destination_pitch
[07:05:41] ========== [PASSED] drm_test_fb_xrgb8888_to_mono ===========
[07:05:41] ==================== drm_test_fb_swab  =====================
[07:05:41] [PASSED] single_pixel_source_buffer
[07:05:41] [PASSED] single_pixel_clip_rectangle
[07:05:41] [PASSED] well_known_colors
[07:05:41] [PASSED] destination_pitch
[07:05:41] ================ [PASSED] drm_test_fb_swab =================
[07:05:41] ============ drm_test_fb_xrgb8888_to_xbgr8888  =============
[07:05:41] [PASSED] single_pixel_source_buffer
[07:05:41] [PASSED] single_pixel_clip_rectangle
[07:05:41] [PASSED] well_known_colors
[07:05:41] [PASSED] destination_pitch
[07:05:41] ======== [PASSED] drm_test_fb_xrgb8888_to_xbgr8888 =========
[07:05:41] ============ drm_test_fb_xrgb8888_to_abgr8888  =============
[07:05:41] [PASSED] single_pixel_source_buffer
[07:05:41] [PASSED] single_pixel_clip_rectangle
[07:05:41] [PASSED] well_known_colors
[07:05:41] [PASSED] destination_pitch
[07:05:41] ======== [PASSED] drm_test_fb_xrgb8888_to_abgr8888 =========
[07:05:41] ================= drm_test_fb_clip_offset  =================
[07:05:41] [PASSED] pass through
[07:05:41] [PASSED] horizontal offset
[07:05:41] [PASSED] vertical offset
[07:05:41] [PASSED] horizontal and vertical offset
[07:05:41] [PASSED] horizontal offset (custom pitch)
[07:05:41] [PASSED] vertical offset (custom pitch)
[07:05:41] [PASSED] horizontal and vertical offset (custom pitch)
[07:05:41] ============= [PASSED] drm_test_fb_clip_offset =============
[07:05:41] =================== drm_test_fb_memcpy  ====================
[07:05:41] [PASSED] single_pixel_source_buffer: XR24 little-endian (0x34325258)
[07:05:41] [PASSED] single_pixel_source_buffer: XRA8 little-endian (0x38415258)
[07:05:41] [PASSED] single_pixel_source_buffer: YU24 little-endian (0x34325559)
[07:05:41] [PASSED] single_pixel_clip_rectangle: XB24 little-endian (0x34324258)
[07:05:41] [PASSED] single_pixel_clip_rectangle: XRA8 little-endian (0x38415258)
[07:05:41] [PASSED] single_pixel_clip_rectangle: YU24 little-endian (0x34325559)
[07:05:41] [PASSED] well_known_colors: XB24 little-endian (0x34324258)
[07:05:41] [PASSED] well_known_colors: XRA8 little-endian (0x38415258)
[07:05:41] [PASSED] well_known_colors: YU24 little-endian (0x34325559)
[07:05:41] [PASSED] destination_pitch: XB24 little-endian (0x34324258)
[07:05:41] [PASSED] destination_pitch: XRA8 little-endian (0x38415258)
[07:05:41] [PASSED] destination_pitch: YU24 little-endian (0x34325559)
[07:05:41] =============== [PASSED] drm_test_fb_memcpy ================
[07:05:41] ============= [PASSED] drm_format_helper_test ==============
[07:05:41] ================= drm_format (18 subtests) =================
[07:05:41] [PASSED] drm_test_format_block_width_invalid
[07:05:41] [PASSED] drm_test_format_block_width_one_plane
[07:05:41] [PASSED] drm_test_format_block_width_two_plane
[07:05:41] [PASSED] drm_test_format_block_width_three_plane
[07:05:41] [PASSED] drm_test_format_block_width_tiled
[07:05:41] [PASSED] drm_test_format_block_height_invalid
[07:05:41] [PASSED] drm_test_format_block_height_one_plane
[07:05:41] [PASSED] drm_test_format_block_height_two_plane
[07:05:41] [PASSED] drm_test_format_block_height_three_plane
[07:05:41] [PASSED] drm_test_format_block_height_tiled
[07:05:41] [PASSED] drm_test_format_min_pitch_invalid
[07:05:41] [PASSED] drm_test_format_min_pitch_one_plane_8bpp
[07:05:41] [PASSED] drm_test_format_min_pitch_one_plane_16bpp
[07:05:41] [PASSED] drm_test_format_min_pitch_one_plane_24bpp
[07:05:41] [PASSED] drm_test_format_min_pitch_one_plane_32bpp
[07:05:41] [PASSED] drm_test_format_min_pitch_two_plane
[07:05:41] [PASSED] drm_test_format_min_pitch_three_plane_8bpp
[07:05:41] [PASSED] drm_test_format_min_pitch_tiled
[07:05:41] =================== [PASSED] drm_format ====================
[07:05:41] ============== drm_framebuffer (10 subtests) ===============
[07:05:41] ========== drm_test_framebuffer_check_src_coords  ==========
[07:05:41] [PASSED] Success: source fits into fb
[07:05:41] [PASSED] Fail: overflowing fb with x-axis coordinate
[07:05:41] [PASSED] Fail: overflowing fb with y-axis coordinate
[07:05:41] [PASSED] Fail: overflowing fb with source width
[07:05:41] [PASSED] Fail: overflowing fb with source height
[07:05:41] ====== [PASSED] drm_test_framebuffer_check_src_coords ======
[07:05:41] [PASSED] drm_test_framebuffer_cleanup
[07:05:41] =============== drm_test_framebuffer_create  ===============
[07:05:41] [PASSED] ABGR8888 normal sizes
[07:05:41] [PASSED] ABGR8888 max sizes
[07:05:41] [PASSED] ABGR8888 pitch greater than min required
[07:05:41] [PASSED] ABGR8888 pitch less than min required
[07:05:41] [PASSED] ABGR8888 Invalid width
[07:05:41] [PASSED] ABGR8888 Invalid buffer handle
[07:05:41] [PASSED] No pixel format
[07:05:41] [PASSED] ABGR8888 Width 0
[07:05:41] [PASSED] ABGR8888 Height 0
[07:05:41] [PASSED] ABGR8888 Out of bound height * pitch combination
[07:05:41] [PASSED] ABGR8888 Large buffer offset
[07:05:41] [PASSED] ABGR8888 Buffer offset for inexistent plane
[07:05:41] [PASSED] ABGR8888 Invalid flag
[07:05:41] [PASSED] ABGR8888 Set DRM_MODE_FB_MODIFIERS without modifiers
[07:05:41] [PASSED] ABGR8888 Valid buffer modifier
[07:05:41] [PASSED] ABGR8888 Invalid buffer modifier(DRM_FORMAT_MOD_SAMSUNG_64_32_TILE)
[07:05:41] [PASSED] ABGR8888 Extra pitches without DRM_MODE_FB_MODIFIERS
[07:05:41] [PASSED] ABGR8888 Extra pitches with DRM_MODE_FB_MODIFIERS
[07:05:41] [PASSED] NV12 Normal sizes
[07:05:41] [PASSED] NV12 Max sizes
[07:05:41] [PASSED] NV12 Invalid pitch
[07:05:41] [PASSED] NV12 Invalid modifier/missing DRM_MODE_FB_MODIFIERS flag
[07:05:41] [PASSED] NV12 different  modifier per-plane
[07:05:41] [PASSED] NV12 with DRM_FORMAT_MOD_SAMSUNG_64_32_TILE
[07:05:41] [PASSED] NV12 Valid modifiers without DRM_MODE_FB_MODIFIERS
[07:05:41] [PASSED] NV12 Modifier for inexistent plane
[07:05:41] [PASSED] NV12 Handle for inexistent plane
[07:05:41] [PASSED] NV12 Handle for inexistent plane without DRM_MODE_FB_MODIFIERS
[07:05:41] [PASSED] YVU420 DRM_MODE_FB_MODIFIERS set without modifier
[07:05:41] [PASSED] YVU420 Normal sizes
[07:05:41] [PASSED] YVU420 Max sizes
[07:05:41] [PASSED] YVU420 Invalid pitch
[07:05:41] [PASSED] YVU420 Different pitches
[07:05:41] [PASSED] YVU420 Different buffer offsets/pitches
[07:05:41] [PASSED] YVU420 Modifier set just for plane 0, without DRM_MODE_FB_MODIFIERS
[07:05:41] [PASSED] YVU420 Modifier set just for planes 0, 1, without DRM_MODE_FB_MODIFIERS
[07:05:41] [PASSED] YVU420 Modifier set just for plane 0, 1, with DRM_MODE_FB_MODIFIERS
[07:05:41] [PASSED] YVU420 Valid modifier
[07:05:41] [PASSED] YVU420 Different modifiers per plane
[07:05:41] [PASSED] YVU420 Modifier for inexistent plane
[07:05:41] [PASSED] YUV420_10BIT Invalid modifier(DRM_FORMAT_MOD_LINEAR)
[07:05:41] [PASSED] X0L2 Normal sizes
[07:05:41] [PASSED] X0L2 Max sizes
[07:05:41] [PASSED] X0L2 Invalid pitch
[07:05:41] [PASSED] X0L2 Pitch greater than minimum required
[07:05:41] [PASSED] X0L2 Handle for inexistent plane
[07:05:41] [PASSED] X0L2 Offset for inexistent plane, without DRM_MODE_FB_MODIFIERS set
[07:05:41] [PASSED] X0L2 Modifier without DRM_MODE_FB_MODIFIERS set
[07:05:41] [PASSED] X0L2 Valid modifier
[07:05:41] [PASSED] X0L2 Modifier for inexistent plane
[07:05:41] =========== [PASSED] drm_test_framebuffer_create ===========
[07:05:41] [PASSED] drm_test_framebuffer_free
[07:05:41] [PASSED] drm_test_framebuffer_init
[07:05:41] [PASSED] drm_test_framebuffer_init_bad_format
[07:05:41] [PASSED] drm_test_framebuffer_init_dev_mismatch
[07:05:41] [PASSED] drm_test_framebuffer_lookup
[07:05:41] [PASSED] drm_test_framebuffer_lookup_inexistent
[07:05:41] [PASSED] drm_test_framebuffer_modifiers_not_supported
[07:05:41] ================= [PASSED] drm_framebuffer =================
[07:05:41] ================ drm_gem_shmem (8 subtests) ================
[07:05:41] [PASSED] drm_gem_shmem_test_obj_create
[07:05:41] [PASSED] drm_gem_shmem_test_obj_create_private
[07:05:41] [PASSED] drm_gem_shmem_test_pin_pages
[07:05:41] [PASSED] drm_gem_shmem_test_vmap
[07:05:41] [PASSED] drm_gem_shmem_test_get_sg_table
[07:05:41] [PASSED] drm_gem_shmem_test_get_pages_sgt
[07:05:41] [PASSED] drm_gem_shmem_test_madvise
[07:05:41] [PASSED] drm_gem_shmem_test_purge
[07:05:41] ================== [PASSED] drm_gem_shmem ==================
[07:05:41] === drm_atomic_helper_connector_hdmi_check (27 subtests) ===
[07:05:41] [PASSED] drm_test_check_broadcast_rgb_auto_cea_mode
[07:05:41] [PASSED] drm_test_check_broadcast_rgb_auto_cea_mode_vic_1
[07:05:41] [PASSED] drm_test_check_broadcast_rgb_full_cea_mode
[07:05:41] [PASSED] drm_test_check_broadcast_rgb_full_cea_mode_vic_1
[07:05:41] [PASSED] drm_test_check_broadcast_rgb_limited_cea_mode
[07:05:41] [PASSED] drm_test_check_broadcast_rgb_limited_cea_mode_vic_1
[07:05:41] ====== drm_test_check_broadcast_rgb_cea_mode_yuv420  =======
[07:05:41] [PASSED] Automatic
[07:05:41] [PASSED] Full
[07:05:41] [PASSED] Limited 16:235
[07:05:41] == [PASSED] drm_test_check_broadcast_rgb_cea_mode_yuv420 ===
[07:05:41] [PASSED] drm_test_check_broadcast_rgb_crtc_mode_changed
[07:05:41] [PASSED] drm_test_check_broadcast_rgb_crtc_mode_not_changed
[07:05:41] [PASSED] drm_test_check_disable_connector
[07:05:41] [PASSED] drm_test_check_hdmi_funcs_reject_rate
[07:05:41] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_rgb
[07:05:41] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_yuv420
[07:05:41] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_ignore_yuv422
[07:05:41] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_ignore_yuv420
[07:05:41] [PASSED] drm_test_check_driver_unsupported_fallback_yuv420
[07:05:41] [PASSED] drm_test_check_output_bpc_crtc_mode_changed
[07:05:41] [PASSED] drm_test_check_output_bpc_crtc_mode_not_changed
[07:05:41] [PASSED] drm_test_check_output_bpc_dvi
[07:05:41] [PASSED] drm_test_check_output_bpc_format_vic_1
[07:05:41] [PASSED] drm_test_check_output_bpc_format_display_8bpc_only
[07:05:41] [PASSED] drm_test_check_output_bpc_format_display_rgb_only
[07:05:41] [PASSED] drm_test_check_output_bpc_format_driver_8bpc_only
[07:05:41] [PASSED] drm_test_check_output_bpc_format_driver_rgb_only
[07:05:41] [PASSED] drm_test_check_tmds_char_rate_rgb_8bpc
[07:05:41] [PASSED] drm_test_check_tmds_char_rate_rgb_10bpc
[07:05:41] [PASSED] drm_test_check_tmds_char_rate_rgb_12bpc
[07:05:41] ===== [PASSED] drm_atomic_helper_connector_hdmi_check ======
[07:05:41] === drm_atomic_helper_connector_hdmi_reset (6 subtests) ====
[07:05:41] [PASSED] drm_test_check_broadcast_rgb_value
[07:05:41] [PASSED] drm_test_check_bpc_8_value
[07:05:41] [PASSED] drm_test_check_bpc_10_value
[07:05:41] [PASSED] drm_test_check_bpc_12_value
[07:05:41] [PASSED] drm_test_check_format_value
[07:05:41] [PASSED] drm_test_check_tmds_char_value
[07:05:41] ===== [PASSED] drm_atomic_helper_connector_hdmi_reset ======
[07:05:41] = drm_atomic_helper_connector_hdmi_mode_valid (4 subtests) =
[07:05:41] [PASSED] drm_test_check_mode_valid
[07:05:41] [PASSED] drm_test_check_mode_valid_reject
[07:05:41] [PASSED] drm_test_check_mode_valid_reject_rate
[07:05:41] [PASSED] drm_test_check_mode_valid_reject_max_clock
[07:05:41] === [PASSED] drm_atomic_helper_connector_hdmi_mode_valid ===
[07:05:41] = drm_atomic_helper_connector_hdmi_infoframes (5 subtests) =
[07:05:41] [PASSED] drm_test_check_infoframes
[07:05:41] [PASSED] drm_test_check_reject_avi_infoframe
[07:05:41] [PASSED] drm_test_check_reject_hdr_infoframe_bpc_8
[07:05:41] [PASSED] drm_test_check_reject_hdr_infoframe_bpc_10
[07:05:41] [PASSED] drm_test_check_reject_audio_infoframe
[07:05:41] === [PASSED] drm_atomic_helper_connector_hdmi_infoframes ===
[07:05:41] ================= drm_managed (2 subtests) =================
[07:05:41] [PASSED] drm_test_managed_release_action
[07:05:41] [PASSED] drm_test_managed_run_action
[07:05:41] =================== [PASSED] drm_managed ===================
[07:05:41] =================== drm_mm (6 subtests) ====================
[07:05:41] [PASSED] drm_test_mm_init
[07:05:41] [PASSED] drm_test_mm_debug
[07:05:41] [PASSED] drm_test_mm_align32
[07:05:41] [PASSED] drm_test_mm_align64
[07:05:41] [PASSED] drm_test_mm_lowest
[07:05:41] [PASSED] drm_test_mm_highest
[07:05:41] ===================== [PASSED] drm_mm ======================
[07:05:41] ============= drm_modes_analog_tv (5 subtests) =============
[07:05:41] [PASSED] drm_test_modes_analog_tv_mono_576i
[07:05:41] [PASSED] drm_test_modes_analog_tv_ntsc_480i
[07:05:41] [PASSED] drm_test_modes_analog_tv_ntsc_480i_inlined
[07:05:41] [PASSED] drm_test_modes_analog_tv_pal_576i
[07:05:41] [PASSED] drm_test_modes_analog_tv_pal_576i_inlined
[07:05:41] =============== [PASSED] drm_modes_analog_tv ===============
[07:05:41] ============== drm_plane_helper (2 subtests) ===============
[07:05:41] =============== drm_test_check_plane_state  ================
[07:05:41] [PASSED] clipping_simple
[07:05:41] [PASSED] clipping_rotate_reflect
[07:05:41] [PASSED] positioning_simple
[07:05:41] [PASSED] upscaling
[07:05:41] [PASSED] downscaling
[07:05:41] [PASSED] rounding1
[07:05:41] [PASSED] rounding2
[07:05:41] [PASSED] rounding3
[07:05:41] [PASSED] rounding4
[07:05:41] =========== [PASSED] drm_test_check_plane_state ============
[07:05:41] =========== drm_test_check_invalid_plane_state  ============
[07:05:41] [PASSED] positioning_invalid
[07:05:41] [PASSED] upscaling_invalid
[07:05:41] [PASSED] downscaling_invalid
[07:05:41] ======= [PASSED] drm_test_check_invalid_plane_state ========
[07:05:41] ================ [PASSED] drm_plane_helper =================
[07:05:41] ====== drm_connector_helper_tv_get_modes (1 subtest) =======
[07:05:41] ====== drm_test_connector_helper_tv_get_modes_check  =======
[07:05:41] [PASSED] None
[07:05:41] [PASSED] PAL
[07:05:41] [PASSED] NTSC
[07:05:41] [PASSED] Both, NTSC Default
[07:05:41] [PASSED] Both, PAL Default
[07:05:41] [PASSED] Both, NTSC Default, with PAL on command-line
[07:05:41] [PASSED] Both, PAL Default, with NTSC on command-line
[07:05:41] == [PASSED] drm_test_connector_helper_tv_get_modes_check ===
[07:05:41] ======== [PASSED] drm_connector_helper_tv_get_modes ========
[07:05:41] ================== drm_rect (9 subtests) ===================
[07:05:41] [PASSED] drm_test_rect_clip_scaled_div_by_zero
[07:05:41] [PASSED] drm_test_rect_clip_scaled_not_clipped
[07:05:41] [PASSED] drm_test_rect_clip_scaled_clipped
[07:05:41] [PASSED] drm_test_rect_clip_scaled_signed_vs_unsigned
[07:05:41] ================= drm_test_rect_intersect  =================
[07:05:41] [PASSED] top-left x bottom-right: 2x2+1+1 x 2x2+0+0
[07:05:41] [PASSED] top-right x bottom-left: 2x2+0+0 x 2x2+1-1
[07:05:41] [PASSED] bottom-left x top-right: 2x2+1-1 x 2x2+0+0
[07:05:41] [PASSED] bottom-right x top-left: 2x2+0+0 x 2x2+1+1
[07:05:41] [PASSED] right x left: 2x1+0+0 x 3x1+1+0
[07:05:41] [PASSED] left x right: 3x1+1+0 x 2x1+0+0
[07:05:41] [PASSED] up x bottom: 1x2+0+0 x 1x3+0-1
[07:05:41] [PASSED] bottom x up: 1x3+0-1 x 1x2+0+0
[07:05:41] [PASSED] touching corner: 1x1+0+0 x 2x2+1+1
[07:05:41] [PASSED] touching side: 1x1+0+0 x 1x1+1+0
[07:05:41] [PASSED] equal rects: 2x2+0+0 x 2x2+0+0
[07:05:41] [PASSED] inside another: 2x2+0+0 x 1x1+1+1
[07:05:41] [PASSED] far away: 1x1+0+0 x 1x1+3+6
[07:05:41] [PASSED] points intersecting: 0x0+5+10 x 0x0+5+10
[07:05:41] [PASSED] points not intersecting: 0x0+0+0 x 0x0+5+10
[07:05:41] ============= [PASSED] drm_test_rect_intersect =============
[07:05:41] ================ drm_test_rect_calc_hscale  ================
[07:05:41] [PASSED] normal use
[07:05:41] [PASSED] out of max range
[07:05:41] [PASSED] out of min range
[07:05:41] [PASSED] zero dst
[07:05:41] [PASSED] negative src
[07:05:41] [PASSED] negative dst
[07:05:41] ============ [PASSED] drm_test_rect_calc_hscale ============
[07:05:41] ================ drm_test_rect_calc_vscale  ================
[07:05:41] [PASSED] normal use
[07:05:41] [PASSED] out of max range
[07:05:41] [PASSED] out of min range
[07:05:41] [PASSED] zero dst
[07:05:41] [PASSED] negative src
[07:05:41] [PASSED] negative dst
stty: 'standard input': Inappropriate ioctl for device
[07:05:41] ============ [PASSED] drm_test_rect_calc_vscale ============
[07:05:41] ================== drm_test_rect_rotate  ===================
[07:05:41] [PASSED] reflect-x
[07:05:41] [PASSED] reflect-y
[07:05:41] [PASSED] rotate-0
[07:05:41] [PASSED] rotate-90
[07:05:41] [PASSED] rotate-180
[07:05:41] [PASSED] rotate-270
[07:05:41] ============== [PASSED] drm_test_rect_rotate ===============
[07:05:41] ================ drm_test_rect_rotate_inv  =================
[07:05:41] [PASSED] reflect-x
[07:05:41] [PASSED] reflect-y
[07:05:41] [PASSED] rotate-0
[07:05:41] [PASSED] rotate-90
[07:05:41] [PASSED] rotate-180
[07:05:41] [PASSED] rotate-270
[07:05:41] ============ [PASSED] drm_test_rect_rotate_inv =============
[07:05:41] ==================== [PASSED] drm_rect =====================
[07:05:41] ============ drm_sysfb_modeset_test (1 subtest) ============
[07:05:41] ============ drm_test_sysfb_build_fourcc_list  =============
[07:05:41] [PASSED] no native formats
[07:05:41] [PASSED] XRGB8888 as native format
[07:05:41] [PASSED] remove duplicates
[07:05:41] [PASSED] convert alpha formats
[07:05:41] [PASSED] random formats
[07:05:41] ======== [PASSED] drm_test_sysfb_build_fourcc_list =========
[07:05:41] ============= [PASSED] drm_sysfb_modeset_test ==============
[07:05:41] ================== drm_fixp (2 subtests) ===================
[07:05:41] [PASSED] drm_test_int2fixp
[07:05:41] [PASSED] drm_test_sm2fixp
[07:05:41] ==================== [PASSED] drm_fixp =====================
[07:05:41] ============================================================
[07:05:41] Testing complete. Ran 621 tests: passed: 621
[07:05:41] Elapsed time: 26.209s total, 1.767s configuring, 24.270s building, 0.141s running

+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/ttm/tests/.kunitconfig
[07:05:41] Configuring KUnit Kernel ...
Regenerating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[07:05:43] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[07:05:52] Starting KUnit Kernel (1/1)...
[07:05:52] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[07:05:53] ================= ttm_device (5 subtests) ==================
[07:05:53] [PASSED] ttm_device_init_basic
[07:05:53] [PASSED] ttm_device_init_multiple
[07:05:53] [PASSED] ttm_device_fini_basic
[07:05:53] [PASSED] ttm_device_init_no_vma_man
[07:05:53] ================== ttm_device_init_pools  ==================
[07:05:53] [PASSED] No DMA allocations, no DMA32 required
[07:05:53] [PASSED] DMA allocations, DMA32 required
[07:05:53] [PASSED] No DMA allocations, DMA32 required
[07:05:53] [PASSED] DMA allocations, no DMA32 required
[07:05:53] ============== [PASSED] ttm_device_init_pools ==============
[07:05:53] =================== [PASSED] ttm_device ====================
[07:05:53] ================== ttm_pool (8 subtests) ===================
[07:05:53] ================== ttm_pool_alloc_basic  ===================
[07:05:53] [PASSED] One page
[07:05:53] [PASSED] More than one page
[07:05:53] [PASSED] Above the allocation limit
[07:05:53] [PASSED] One page, with coherent DMA mappings enabled
[07:05:53] [PASSED] Above the allocation limit, with coherent DMA mappings enabled
[07:05:53] ============== [PASSED] ttm_pool_alloc_basic ===============
[07:05:53] ============== ttm_pool_alloc_basic_dma_addr  ==============
[07:05:53] [PASSED] One page
[07:05:53] [PASSED] More than one page
[07:05:53] [PASSED] Above the allocation limit
[07:05:53] [PASSED] One page, with coherent DMA mappings enabled
[07:05:53] [PASSED] Above the allocation limit, with coherent DMA mappings enabled
[07:05:53] ========== [PASSED] ttm_pool_alloc_basic_dma_addr ==========
[07:05:53] [PASSED] ttm_pool_alloc_order_caching_match
[07:05:53] [PASSED] ttm_pool_alloc_caching_mismatch
[07:05:53] [PASSED] ttm_pool_alloc_order_mismatch
[07:05:53] [PASSED] ttm_pool_free_dma_alloc
[07:05:53] [PASSED] ttm_pool_free_no_dma_alloc
[07:05:53] [PASSED] ttm_pool_fini_basic
[07:05:53] ==================== [PASSED] ttm_pool =====================
[07:05:53] ================ ttm_resource (8 subtests) =================
[07:05:53] ================= ttm_resource_init_basic  =================
[07:05:53] [PASSED] Init resource in TTM_PL_SYSTEM
[07:05:53] [PASSED] Init resource in TTM_PL_VRAM
[07:05:53] [PASSED] Init resource in a private placement
[07:05:53] [PASSED] Init resource in TTM_PL_SYSTEM, set placement flags
[07:05:53] ============= [PASSED] ttm_resource_init_basic =============
[07:05:53] [PASSED] ttm_resource_init_pinned
[07:05:53] [PASSED] ttm_resource_fini_basic
[07:05:53] [PASSED] ttm_resource_manager_init_basic
[07:05:53] [PASSED] ttm_resource_manager_usage_basic
[07:05:53] [PASSED] ttm_resource_manager_set_used_basic
[07:05:53] [PASSED] ttm_sys_man_alloc_basic
[07:05:53] [PASSED] ttm_sys_man_free_basic
[07:05:53] ================== [PASSED] ttm_resource ===================
[07:05:53] =================== ttm_tt (15 subtests) ===================
[07:05:53] ==================== ttm_tt_init_basic  ====================
[07:05:53] [PASSED] Page-aligned size
[07:05:53] [PASSED] Extra pages requested
[07:05:53] ================ [PASSED] ttm_tt_init_basic ================
[07:05:53] [PASSED] ttm_tt_init_misaligned
[07:05:53] [PASSED] ttm_tt_fini_basic
[07:05:53] [PASSED] ttm_tt_fini_sg
[07:05:53] [PASSED] ttm_tt_fini_shmem
[07:05:53] [PASSED] ttm_tt_create_basic
[07:05:53] [PASSED] ttm_tt_create_invalid_bo_type
[07:05:53] [PASSED] ttm_tt_create_ttm_exists
[07:05:53] [PASSED] ttm_tt_create_failed
[07:05:53] [PASSED] ttm_tt_destroy_basic
[07:05:53] [PASSED] ttm_tt_populate_null_ttm
[07:05:53] [PASSED] ttm_tt_populate_populated_ttm
[07:05:53] [PASSED] ttm_tt_unpopulate_basic
[07:05:53] [PASSED] ttm_tt_unpopulate_empty_ttm
[07:05:53] [PASSED] ttm_tt_swapin_basic
[07:05:53] ===================== [PASSED] ttm_tt ======================
[07:05:53] =================== ttm_bo (14 subtests) ===================
[07:05:53] =========== ttm_bo_reserve_optimistic_no_ticket  ===========
[07:05:53] [PASSED] Cannot be interrupted and sleeps
[07:05:53] [PASSED] Cannot be interrupted, locks straight away
[07:05:53] [PASSED] Can be interrupted, sleeps
[07:05:53] ======= [PASSED] ttm_bo_reserve_optimistic_no_ticket =======
[07:05:53] [PASSED] ttm_bo_reserve_locked_no_sleep
[07:05:53] [PASSED] ttm_bo_reserve_no_wait_ticket
[07:05:53] [PASSED] ttm_bo_reserve_double_resv
[07:05:53] [PASSED] ttm_bo_reserve_interrupted
[07:05:53] [PASSED] ttm_bo_reserve_deadlock
[07:05:53] [PASSED] ttm_bo_unreserve_basic
[07:05:53] [PASSED] ttm_bo_unreserve_pinned
[07:05:53] [PASSED] ttm_bo_unreserve_bulk
[07:05:53] [PASSED] ttm_bo_fini_basic
[07:05:53] [PASSED] ttm_bo_fini_shared_resv
[07:05:53] [PASSED] ttm_bo_pin_basic
[07:05:53] [PASSED] ttm_bo_pin_unpin_resource
[07:05:53] [PASSED] ttm_bo_multiple_pin_one_unpin
[07:05:53] ===================== [PASSED] ttm_bo ======================
[07:05:53] ============== ttm_bo_validate (22 subtests) ===============
[07:05:53] ============== ttm_bo_init_reserved_sys_man  ===============
[07:05:53] [PASSED] Buffer object for userspace
[07:05:53] [PASSED] Kernel buffer object
[07:05:53] [PASSED] Shared buffer object
[07:05:53] ========== [PASSED] ttm_bo_init_reserved_sys_man ===========
[07:05:53] ============== ttm_bo_init_reserved_mock_man  ==============
[07:05:53] [PASSED] Buffer object for userspace
[07:05:53] [PASSED] Kernel buffer object
[07:05:53] [PASSED] Shared buffer object
[07:05:53] ========== [PASSED] ttm_bo_init_reserved_mock_man ==========
[07:05:53] [PASSED] ttm_bo_init_reserved_resv
[07:05:53] ================== ttm_bo_validate_basic  ==================
[07:05:53] [PASSED] Buffer object for userspace
[07:05:53] [PASSED] Kernel buffer object
[07:05:53] [PASSED] Shared buffer object
[07:05:53] ============== [PASSED] ttm_bo_validate_basic ==============
[07:05:53] [PASSED] ttm_bo_validate_invalid_placement
[07:05:53] ============= ttm_bo_validate_same_placement  ==============
[07:05:53] [PASSED] System manager
[07:05:53] [PASSED] VRAM manager
[07:05:53] ========= [PASSED] ttm_bo_validate_same_placement ==========
[07:05:53] [PASSED] ttm_bo_validate_failed_alloc
[07:05:53] [PASSED] ttm_bo_validate_pinned
[07:05:53] [PASSED] ttm_bo_validate_busy_placement
[07:05:53] ================ ttm_bo_validate_multihop  =================
[07:05:53] [PASSED] Buffer object for userspace
[07:05:53] [PASSED] Kernel buffer object
[07:05:53] [PASSED] Shared buffer object
[07:05:53] ============ [PASSED] ttm_bo_validate_multihop =============
[07:05:53] ========== ttm_bo_validate_no_placement_signaled  ==========
[07:05:53] [PASSED] Buffer object in system domain, no page vector
[07:05:53] [PASSED] Buffer object in system domain with an existing page vector
[07:05:53] ====== [PASSED] ttm_bo_validate_no_placement_signaled ======
[07:05:53] ======== ttm_bo_validate_no_placement_not_signaled  ========
[07:05:53] [PASSED] Buffer object for userspace
[07:05:53] [PASSED] Kernel buffer object
[07:05:53] [PASSED] Shared buffer object
[07:05:53] ==== [PASSED] ttm_bo_validate_no_placement_not_signaled ====
[07:05:53] [PASSED] ttm_bo_validate_move_fence_signaled
[07:05:53] ========= ttm_bo_validate_move_fence_not_signaled  =========
[07:05:53] [PASSED] Waits for GPU
[07:05:53] [PASSED] Tries to lock straight away
[07:05:53] ===== [PASSED] ttm_bo_validate_move_fence_not_signaled =====
[07:05:53] [PASSED] ttm_bo_validate_swapout
[07:05:53] [PASSED] ttm_bo_validate_happy_evict
[07:05:53] [PASSED] ttm_bo_validate_all_pinned_evict
[07:05:53] [PASSED] ttm_bo_validate_allowed_only_evict
[07:05:53] [PASSED] ttm_bo_validate_deleted_evict
[07:05:53] [PASSED] ttm_bo_validate_busy_domain_evict
[07:05:53] [PASSED] ttm_bo_validate_evict_gutting
[07:05:53] [PASSED] ttm_bo_validate_recrusive_evict
stty: 'standard input': Inappropriate ioctl for device
[07:05:53] ================= [PASSED] ttm_bo_validate =================
[07:05:53] ============================================================
[07:05:53] Testing complete. Ran 102 tests: passed: 102
[07:05:53] Elapsed time: 11.328s total, 1.747s configuring, 9.365s building, 0.179s running

+ cleanup
++ stat -c %u:%g /kernel
+ chown -R 1003:1003 /kernel

✓ Xe.CI.BAT: success for drm/i915: move more display dependencies from i915 (rev2)

[Patchwork]

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== Series Details ==

Series: drm/i915: move more display dependencies from i915 (rev2)
URL   : https://patchwork.freedesktop.org/series/163785/
State : success

== Summary ==

CI Bug Log - changes from xe-4838-f1d4727d10d243dfe9253bc650258827a8a7dbb8_BAT -> xe-pw-163785v2_BAT
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  

Participating hosts (14 -> 14)
------------------------------

  No changes in participating hosts

Known issues
------------

  Here are the changes found in xe-pw-163785v2_BAT that come from known issues:

### IGT changes ###

#### Possible fixes ####

  * igt@xe_waitfence@engine:
    - bat-dg2-oem2:       [FAIL][1] ([Intel XE#6519]) -> [PASS][2]
   [1]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4838-f1d4727d10d243dfe9253bc650258827a8a7dbb8/bat-dg2-oem2/igt@xe_waitfence@engine.html
   [2]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-163785v2/bat-dg2-oem2/igt@xe_waitfence@engine.html

  
  [Intel XE#6519]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6519


Build changes
-------------

  * Linux: xe-4838-f1d4727d10d243dfe9253bc650258827a8a7dbb8 -> xe-pw-163785v2

  IGT_8842: 8842
  xe-4838-f1d4727d10d243dfe9253bc650258827a8a7dbb8: f1d4727d10d243dfe9253bc650258827a8a7dbb8
  xe-pw-163785v2: 163785v2

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-163785v2/index.html

[-- Attachment #2: Type: text/html, Size: 1987 bytes --]

✓ Xe.CI.FULL: success for drm/i915: move more display dependencies from i915 (rev2)

[Patchwork]

[-- Attachment #1: Type: text/plain, Size: 1950 bytes --]

== Series Details ==

Series: drm/i915: move more display dependencies from i915 (rev2)
URL   : https://patchwork.freedesktop.org/series/163785/
State : success

== Summary ==

CI Bug Log - changes from xe-4838-f1d4727d10d243dfe9253bc650258827a8a7dbb8_FULL -> xe-pw-163785v2_FULL
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  

Participating hosts (2 -> 2)
------------------------------

  No changes in participating hosts

Known issues
------------

  Here are the changes found in xe-pw-163785v2_FULL that come from known issues:

### IGT changes ###

#### Possible fixes ####

  * igt@kms_flip@flip-vs-expired-vblank@b-edp1:
    - shard-lnl:          [FAIL][1] ([Intel XE#301]) -> [PASS][2] +1 other test pass
   [1]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4838-f1d4727d10d243dfe9253bc650258827a8a7dbb8/shard-lnl-8/igt@kms_flip@flip-vs-expired-vblank@b-edp1.html
   [2]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-163785v2/shard-lnl-4/igt@kms_flip@flip-vs-expired-vblank@b-edp1.html

  * igt@kms_vrr@cmrr@pipe-a-edp-1:
    - shard-lnl:          [FAIL][3] ([Intel XE#4459]) -> [PASS][4] +1 other test pass
   [3]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4838-f1d4727d10d243dfe9253bc650258827a8a7dbb8/shard-lnl-1/igt@kms_vrr@cmrr@pipe-a-edp-1.html
   [4]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-163785v2/shard-lnl-3/igt@kms_vrr@cmrr@pipe-a-edp-1.html

  
  [Intel XE#301]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/301
  [Intel XE#4459]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4459


Build changes
-------------

  * Linux: xe-4838-f1d4727d10d243dfe9253bc650258827a8a7dbb8 -> xe-pw-163785v2

  IGT_8842: 8842
  xe-4838-f1d4727d10d243dfe9253bc650258827a8a7dbb8: f1d4727d10d243dfe9253bc650258827a8a7dbb8
  xe-pw-163785v2: 163785v2

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-163785v2/index.html

[-- Attachment #2: Type: text/html, Size: 2550 bytes --]

RE: [PATCH v2 1/8] drm/i915: move SKL clock gating init to display

[Kandpal, Suraj]

> -----Original Message-----
> From: Intel-gfx <intel-gfx-bounces@lists.freedesktop.org> On Behalf Of Luca
> Coelho
> Sent: Tuesday, March 31, 2026 5:37 PM
> To: intel-gfx@lists.freedesktop.org
> Cc: intel-xe@lists.freedesktop.org; jani.nikula@linux.intel.com;
> ville.syrjala@linux.intel.com
> Subject: [PATCH v2 1/8] drm/i915: move SKL clock gating init to display
> 
> Move the SKL-specific display clock gating programming into a new file inside
> display.
> 
> This removes dependency from intel_clock_gating.c to the display's intel_pch.h
> file, so we can remove the include statement.
> 
> Signed-off-by: Luca Coelho <luciano.coelho@intel.com>
> ---
>  drivers/gpu/drm/i915/Makefile                 |  1 +
>  .../i915/display/intel_display_clock_gating.c | 19 +++++++++++++++++++
> .../i915/display/intel_display_clock_gating.h | 13 +++++++++++++
>  drivers/gpu/drm/i915/intel_clock_gating.c     |  8 ++------
>  4 files changed, 35 insertions(+), 6 deletions(-)  create mode 100644
> drivers/gpu/drm/i915/display/intel_display_clock_gating.c
>  create mode 100644
> drivers/gpu/drm/i915/display/intel_display_clock_gating.h
> 
> diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
> index b677720a1c2d..63a9e16826a9 100644
> --- a/drivers/gpu/drm/i915/Makefile
> +++ b/drivers/gpu/drm/i915/Makefile
> @@ -255,6 +255,7 @@ i915-y += \
>  	display/intel_cursor.o \
>  	display/intel_dbuf_bw.o \
>  	display/intel_de.o \
> +	display/intel_display_clock_gating.o \
>  	display/intel_display.o \
>  	display/intel_display_conversion.o \
>  	display/intel_display_driver.o \
> diff --git a/drivers/gpu/drm/i915/display/intel_display_clock_gating.c
> b/drivers/gpu/drm/i915/display/intel_display_clock_gating.c
> new file mode 100644
> index 000000000000..4a94593335e0
> --- /dev/null
> +++ b/drivers/gpu/drm/i915/display/intel_display_clock_gating.c
> @@ -0,0 +1,19 @@
> +// SPDX-License-Identifier: MIT
> +/*
> + * Copyright 2026 Intel Corporation
> + */
> +
> +#include <drm/intel/intel_gmd_misc_regs.h>
> +
> +#include "intel_de.h"
> +#include "intel_display_clock_gating.h"
> +#include "intel_display_regs.h"
> +
> +void intel_display_skl_init_clock_gating(struct intel_display *display)
> +{
> +	/*
> +	 * WaFbcTurnOffFbcWatermark:skl
> +	 * Display WA #0562: skl
> +	 */
> +	intel_de_rmw(display, DISP_ARB_CTL, 0, DISP_FBC_WM_DIS); }

Not sure about this being moved here but I feel like this belong in intel_display_wa.c see that it is a WA

Regards,
Suraj Kandpal

> diff --git a/drivers/gpu/drm/i915/display/intel_display_clock_gating.h
> b/drivers/gpu/drm/i915/display/intel_display_clock_gating.h
> new file mode 100644
> index 000000000000..00f416db7f47
> --- /dev/null
> +++ b/drivers/gpu/drm/i915/display/intel_display_clock_gating.h
> @@ -0,0 +1,13 @@
> +/* SPDX-License-Identifier: MIT */
> +/*
> + * Copyright 2026 Intel Corporation
> + */
> +
> +#ifndef __INTEL_DISPLAY_CLOCK_GATING_H__ #define
> +__INTEL_DISPLAY_CLOCK_GATING_H__
> +
> +struct intel_display;
> +
> +void intel_display_skl_init_clock_gating(struct intel_display
> +*display);
> +
> +#endif /* __INTEL_DISPLAY_CLOCK_GATING_H__ */
> diff --git a/drivers/gpu/drm/i915/intel_clock_gating.c
> b/drivers/gpu/drm/i915/intel_clock_gating.c
> index ee2489a2fbe7..454334fef5e7 100644
> --- a/drivers/gpu/drm/i915/intel_clock_gating.c
> +++ b/drivers/gpu/drm/i915/intel_clock_gating.c
> @@ -31,9 +31,9 @@
> 
>  #include "display/i9xx_plane_regs.h"
>  #include "display/intel_display.h"
> +#include "display/intel_display_clock_gating.h"
>  #include "display/intel_display_core.h"
>  #include "display/intel_display_regs.h"
> -#include "display/intel_pch.h"
>  #include "gt/intel_engine_regs.h"
>  #include "gt/intel_gt.h"
>  #include "gt/intel_gt_mcr.h"
> @@ -349,11 +349,7 @@ static void skl_init_clock_gating(struct
> drm_i915_private *i915)
>  	/* WAC6entrylatency:skl */
>  	intel_uncore_rmw(&i915->uncore, FBC_LLC_READ_CTRL, 0,
> FBC_LLC_FULLY_OPEN);
> 
> -	/*
> -	 * WaFbcTurnOffFbcWatermark:skl
> -	 * Display WA #0562: skl
> -	 */
> -	intel_uncore_rmw(&i915->uncore, DISP_ARB_CTL, 0,
> DISP_FBC_WM_DIS);
> +	intel_display_skl_init_clock_gating(i915->display);
>  }
> 
>  static void bdw_init_clock_gating(struct drm_i915_private *i915)
> --
> 2.53.0

RE: [PATCH v2 1/8] drm/i915: move SKL clock gating init to display

[Jani Nikula]

On Tue, 07 Apr 2026, "Kandpal, Suraj" <suraj.kandpal@intel.com> wrote:
>> +void intel_display_skl_init_clock_gating(struct intel_display *display)
>> +{
>> +	/*
>> +	 * WaFbcTurnOffFbcWatermark:skl
>> +	 * Display WA #0562: skl
>> +	 */
>> +	intel_de_rmw(display, DISP_ARB_CTL, 0, DISP_FBC_WM_DIS); }
>
> Not sure about this being moved here but I feel like this belong in
> intel_display_wa.c see that it is a WA

A lot of intel_clock_gating.c is about workarounds, and I don't really
care a whole lot about moving these to intel_display_wa.c at this
point. It's much more important to move the display related things from
i915 core to display.

BR,
Jani.


-- 
Jani Nikula, Intel

Re: [PATCH v2 1/8] drm/i915: move SKL clock gating init to display

[Ville Syrjälä]

On Tue, Apr 07, 2026 at 10:58:13AM +0300, Jani Nikula wrote:
> On Tue, 07 Apr 2026, "Kandpal, Suraj" <suraj.kandpal@intel.com> wrote:
> >> +void intel_display_skl_init_clock_gating(struct intel_display *display)
> >> +{
> >> +	/*
> >> +	 * WaFbcTurnOffFbcWatermark:skl
> >> +	 * Display WA #0562: skl
> >> +	 */
> >> +	intel_de_rmw(display, DISP_ARB_CTL, 0, DISP_FBC_WM_DIS); }
> >
> > Not sure about this being moved here but I feel like this belong in
> > intel_display_wa.c see that it is a WA
> 
> A lot of intel_clock_gating.c is about workarounds, and I don't really
> care a whole lot about moving these to intel_display_wa.c at this
> point. It's much more important to move the display related things from
> i915 core to display.

I still think it would have been much easier to move the gt stuff out
from init_clock_gating to the proper place in the gt code. And then we
could have just moved the remaining things into the display code as is.
But people seem to prefer the hard way for some reason :)

-- 
Ville Syrjälä
Intel

Re: [PATCH v2 1/8] drm/i915: move SKL clock gating init to display

[Jani Nikula]

On Tue, 07 Apr 2026, Ville Syrjälä <ville.syrjala@linux.intel.com> wrote:
> On Tue, Apr 07, 2026 at 10:58:13AM +0300, Jani Nikula wrote:
>> On Tue, 07 Apr 2026, "Kandpal, Suraj" <suraj.kandpal@intel.com> wrote:
>> >> +void intel_display_skl_init_clock_gating(struct intel_display *display)
>> >> +{
>> >> +	/*
>> >> +	 * WaFbcTurnOffFbcWatermark:skl
>> >> +	 * Display WA #0562: skl
>> >> +	 */
>> >> +	intel_de_rmw(display, DISP_ARB_CTL, 0, DISP_FBC_WM_DIS); }
>> >
>> > Not sure about this being moved here but I feel like this belong in
>> > intel_display_wa.c see that it is a WA
>> 
>> A lot of intel_clock_gating.c is about workarounds, and I don't really
>> care a whole lot about moving these to intel_display_wa.c at this
>> point. It's much more important to move the display related things from
>> i915 core to display.
>
> I still think it would have been much easier to move the gt stuff out
> from init_clock_gating to the proper place in the gt code. And then we
> could have just moved the remaining things into the display code as is.
> But people seem to prefer the hard way for some reason :)

Whatever gets us there. I'm just saying nitpicking between different
places within display/ isn't helping us.

BR,
Jani.


-- 
Jani Nikula, Intel