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From: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
To: "Nirmoy Das" <nirmoy.das@intel.com>,
	"Thomas Hellström" <thomas.hellstrom@linux.intel.com>,
	intel-xe@lists.freedesktop.org
Cc: Matthew Auld <matthew.auld@intel.com>,
	Matthew Brost <matthew.brost@intel.com>
Subject: Re: [PATCH 1/2] drm/xe: Skip CCS clear for WB type BOs
Date: Wed, 28 Aug 2024 10:36:10 +0200	[thread overview]
Message-ID: <3cf2381e-821a-4229-af06-c38a1d6d3435@linux.intel.com> (raw)
In-Reply-To: <2fbd6036-b010-4fa3-8365-be193ea52008@intel.com>

Hey,

Den 2024-08-28 kl. 10:34, skrev Nirmoy Das:
> 
> On 8/28/2024 10:23 AM, Thomas Hellström wrote:
>> Hi,
>>
>> On Tue, 2024-08-27 at 17:49 +0200, Nirmoy Das wrote:
>>> HW treats any access to 1-way or 2-way coherent memory as compression
>>> disabled memory. So for such BOs there is no need to do CCS clearing.
>>>
>>> Cc: Matthew Auld <matthew.auld@intel.com>
>>> Cc: Matthew Brost <matthew.brost@intel.com>
>>> Cc: Thomas Hellström <thomas.hellstrom@linux.intel.com>
>>> Signed-off-by: Nirmoy Das <nirmoy.das@intel.com>
>>> ---
>>>   drivers/gpu/drm/xe/xe_bo.c | 8 +++++++-
>>>   1 file changed, 7 insertions(+), 1 deletion(-)
>>>
>>> diff --git a/drivers/gpu/drm/xe/xe_bo.c b/drivers/gpu/drm/xe/xe_bo.c
>>> index cbe7bf098970..24701272e3af 100644
>>> --- a/drivers/gpu/drm/xe/xe_bo.c
>>> +++ b/drivers/gpu/drm/xe/xe_bo.c
>>> @@ -283,6 +283,7 @@ struct xe_ttm_tt {
>>>       struct device *dev;
>>>       struct sg_table sgt;
>>>       struct sg_table *sg;
>>> +    bool skip_ccs_clear:1;
>>>   };
>>>     static int xe_tt_map_sg(struct ttm_tt *tt)
>>> @@ -404,6 +405,8 @@ static struct ttm_tt *xe_ttm_tt_create(struct
>>> ttm_buffer_object *ttm_bo,
>>>       if (ttm_bo->type == ttm_bo_type_device && xe-
>>>> mem.gpu_page_clear_sys)
>>>           page_flags |= TTM_TT_FLAG_CLEARED_ON_FREE;
>>>   +    /* compression is not allowed for cached BO so ccs clear can
>>> be skipped. */
>>> +    tt->skip_ccs_clear = caching == ttm_cached;
>> In theory, BOs that are promoted to fb (not created with the SCANOUT
>> flag) can AFAICT have caching remaining at ttm_cached, yet still sent
>> to the display engine, reading uninitialized ccs.
>>
>> Also I think LNL will be the only HW having the "feature" that clean
>> cache-lines are written back so in the future we might allow 0-coherent
>> with ttm_cached.
> 
> 
> I Just read that no compression for 1,2-way coherent is only for LNL In seems so this is mainly applicable for LNL.
> 
> 
>>
>> So IMO we need to improve the detection of "skip_ccs_clear" here.
> 
> 
> How do I detect when a BO is promoted to FB ?
Either check if scanout flag is set, or just unset that flag in pin_fb. :)

Cheers,
~Maarten

  reply	other threads:[~2024-08-28  8:36 UTC|newest]

Thread overview: 17+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2024-08-27 15:49 [PATCH 1/2] drm/xe: Skip CCS clear for WB type BOs Nirmoy Das
2024-08-27 15:49 ` [PATCH 2/2] Revert "drm/xe/lnl: Offload system clear page activity to GPU" Nirmoy Das
2024-08-27 19:49   ` Matthew Brost
2024-08-28  8:24     ` Nirmoy Das
2024-08-27 16:27 ` ✓ CI.Patch_applied: success for series starting with [1/2] drm/xe: Skip CCS clear for WB type BOs Patchwork
2024-08-27 16:28 ` ✓ CI.checkpatch: " Patchwork
2024-08-27 16:29 ` ✓ CI.KUnit: " Patchwork
2024-08-27 16:41 ` ✓ CI.Build: " Patchwork
2024-08-27 16:43 ` ✓ CI.Hooks: " Patchwork
2024-08-27 16:45 ` ✓ CI.checksparse: " Patchwork
2024-08-27 17:04 ` ✓ CI.BAT: " Patchwork
2024-08-28  1:16 ` ✗ CI.FULL: failure " Patchwork
2024-08-28  8:23 ` [PATCH 1/2] " Thomas Hellström
2024-08-28  8:34   ` Nirmoy Das
2024-08-28  8:36     ` Maarten Lankhorst [this message]
2024-08-28  9:31 ` Jani Nikula
2024-08-28 12:09   ` Nirmoy Das

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