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mx.microsoft.com 1; spf=pass smtp.mailfrom=intel.com; dmarc=pass action=none header.from=intel.com; dkim=pass header.d=intel.com; arc=none Authentication-Results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=intel.com; Received: from DM4PR11MB5341.namprd11.prod.outlook.com (2603:10b6:5:390::22) by PH8PR11MB6952.namprd11.prod.outlook.com (2603:10b6:510:224::13) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.9366.15; Fri, 28 Nov 2025 13:33:04 +0000 Received: from DM4PR11MB5341.namprd11.prod.outlook.com ([fe80::397:7566:d626:e839]) by DM4PR11MB5341.namprd11.prod.outlook.com ([fe80::397:7566:d626:e839%7]) with mapi id 15.20.9366.012; Fri, 28 Nov 2025 13:33:04 +0000 Message-ID: <41b8f2f1-39a8-44a4-a298-58e76bf07331@intel.com> Date: Fri, 28 Nov 2025 19:02:58 +0530 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v9 09/17] drm/i915/display: Add DC Balance flip count operations To: Mitul Golani , CC: , References: <20251127091614.648791-1-mitulkumar.ajitkumar.golani@intel.com> <20251127091614.648791-10-mitulkumar.ajitkumar.golani@intel.com> Content-Language: en-US From: "Nautiyal, Ankit K" In-Reply-To: <20251127091614.648791-10-mitulkumar.ajitkumar.golani@intel.com> Content-Type: text/plain; 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Increment > DC Balance Flip count before every flip to indicate DMC > firmware about new flip occurrence which needs to be adjusted > for dc balancing. This is tracked separately from legacy > FLIP_COUNT register also Reset DC balance flip count value > while disabling VRR adaptive mode, this is to start with > fresh counts when VRR adaptive refresh mode is triggered again. > > --v2: > - Call during intel_update_crtc.(Ankit) > > Signed-off-by: Mitul Golani Reviewed-by: Ankit Nautiyal > --- > drivers/gpu/drm/i915/display/intel_display.c | 3 +++ > .../gpu/drm/i915/display/intel_display_types.h | 4 ++++ > drivers/gpu/drm/i915/display/intel_vrr.c | 15 +++++++++++++++ > drivers/gpu/drm/i915/display/intel_vrr.h | 2 ++ > 4 files changed, 24 insertions(+) > > diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c > index d41ab965c013..1269f841d48b 100644 > --- a/drivers/gpu/drm/i915/display/intel_display.c > +++ b/drivers/gpu/drm/i915/display/intel_display.c > @@ -6863,6 +6863,9 @@ static void intel_update_crtc(struct intel_atomic_state *state, > intel_crtc_update_active_timings(new_crtc_state, > new_crtc_state->vrr.enable); > > + if (new_crtc_state->vrr.dc_balance.enable) > + intel_vrr_dcb_increment_flip_count(new_crtc_state, crtc); > + > /* > * We usually enable FIFO underrun interrupts as part of the > * CRTC enable sequence during modesets. But when we inherit a > diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h > index 8eb0ace7d918..740c5fc9fe1e 100644 > --- a/drivers/gpu/drm/i915/display/intel_display_types.h > +++ b/drivers/gpu/drm/i915/display/intel_display_types.h > @@ -1501,6 +1501,10 @@ struct intel_crtc { > struct intel_link_m_n m_n, m2_n2; > } drrs; > > + struct { > + u64 flip_count; > + } dc_balance; > + > int scanline_offset; > > struct { > diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c > index ff65c1167e1b..411ae5da3824 100644 > --- a/drivers/gpu/drm/i915/display/intel_vrr.c > +++ b/drivers/gpu/drm/i915/display/intel_vrr.c > @@ -632,6 +632,20 @@ void intel_vrr_set_transcoder_timings(const struct intel_crtc_state *crtc_state) > EMP_AS_SDP_DB_TL(crtc_state->vrr.vsync_start)); > } > > +void > +intel_vrr_dcb_increment_flip_count(struct intel_crtc_state *crtc_state, > + struct intel_crtc *crtc) > +{ > + struct intel_display *display = to_intel_display(crtc_state); > + enum pipe pipe = crtc->pipe; > + > + if (!crtc_state->vrr.dc_balance.enable) > + return; > + > + intel_de_write(display, PIPEDMC_DCB_FLIP_COUNT(pipe), > + ++crtc->dc_balance.flip_count); > +} > + > void > intel_vrr_dcb_reset(const struct intel_crtc_state *old_crtc_state, > struct intel_crtc *crtc) > @@ -642,6 +656,7 @@ intel_vrr_dcb_reset(const struct intel_crtc_state *old_crtc_state, > if (!old_crtc_state->vrr.dc_balance.enable) > return; > > + intel_de_write(display, PIPEDMC_DCB_FLIP_COUNT(pipe), 0); > intel_de_write(display, PIPEDMC_DCB_BALANCE_RESET(pipe), 0); > } > > diff --git a/drivers/gpu/drm/i915/display/intel_vrr.h b/drivers/gpu/drm/i915/display/intel_vrr.h > index d40ed5504180..bedcc8c4bff2 100644 > --- a/drivers/gpu/drm/i915/display/intel_vrr.h > +++ b/drivers/gpu/drm/i915/display/intel_vrr.h > @@ -29,6 +29,8 @@ void intel_vrr_send_push(struct intel_dsb *dsb, > const struct intel_crtc_state *crtc_state); > void intel_vrr_check_push_sent(struct intel_dsb *dsb, > const struct intel_crtc_state *crtc_state); > +void intel_vrr_dcb_increment_flip_count(struct intel_crtc_state *crtc_state, > + struct intel_crtc *crtc); > bool intel_vrr_is_push_sent(const struct intel_crtc_state *crtc_state); > void intel_vrr_disable(const struct intel_crtc_state *old_crtc_state); > void intel_vrr_get_config(struct intel_crtc_state *crtc_state);