Re: [PATCH 05/11] drm/i915: Extract intel_plane_needs_low_address()

Jani Nikula
2026-04-17T09:43:39Z

On Thu, 16 Apr 2026, Ville Syrjala <ville.syrjala@linux.intel.com> wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Extract the naked "gmch? -> need a low ggtt address" check into
> a more descriptive helper (intel_plane_needs_low_address()).
> The goal being to eliminate all display specific stuff from the
> low level pinning code.
>
> The actual implementation still abuses PIN_MAPPABLE to achieve
> this goal. I'm not entire convinced that this whole thing even
> needs to exist, and the original issue wasn't just caused by
> some other bug. But no time to dig into it right now, so let's
> keep going.
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

Reviewed-by: Jani Nikula <jani.nikula@intel.com>

> ---
> drivers/gpu/drm/i915/display/intel_plane.c | 13 +++++++++++++
> drivers/gpu/drm/i915/display/intel_plane.h | 2 ++
> drivers/gpu/drm/i915/i915_fb_pin.c | 11 ++---------
> 3 files changed, 17 insertions(+), 9 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_plane.c b/drivers/gpu/drm/i915/display/intel_plane.c
> index f15dd9e91243..f41f4c2ac320 100644
> --- a/drivers/gpu/drm/i915/display/intel_plane.c
> +++ b/drivers/gpu/drm/i915/display/intel_plane.c
> @@ -171,6 +171,19 @@ intel_plane_destroy_state(struct drm_plane *plane,
> kfree(plane_state);
> }
>
> +bool intel_plane_needs_low_address(struct intel_display *display)
> +{
> + /*
> + * Valleyview is definitely limited to scanning out the first
> + * 512MiB. Lets presume this behaviour was inherited from the
> + * g4x display engine and that all earlier gen are similarly
> + * limited. Testing suggests that it is a little more
> + * complicated than this. For example, Cherryview appears quite
> + * happy to scanout from anywhere within its global aperture.
> + */
> + return HAS_GMCH(display);
> +}
> +
> bool intel_plane_needs_physical(struct intel_plane *plane)
> {
> struct intel_display *display = to_intel_display(plane);
> diff --git a/drivers/gpu/drm/i915/display/intel_plane.h b/drivers/gpu/drm/i915/display/intel_plane.h
> index 5a8f2f3baab5..7fa7fbbb58dc 100644
> --- a/drivers/gpu/drm/i915/display/intel_plane.h
> +++ b/drivers/gpu/drm/i915/display/intel_plane.h
> @@ -15,6 +15,7 @@ struct drm_rect;
> struct intel_atomic_state;
> struct intel_crtc;
> struct intel_crtc_state;
> +struct intel_display;
> struct intel_dsb;
> struct intel_plane;
> struct intel_plane_state;
> @@ -79,6 +80,7 @@ int intel_plane_check_src_coordinates(struct intel_plane_state *plane_state);
> void intel_plane_set_invisible(struct intel_crtc_state *crtc_state,
> struct intel_plane_state *plane_state);
> void intel_plane_helper_add(struct intel_plane *plane);
> +bool intel_plane_needs_low_address(struct intel_display *display);
> bool intel_plane_needs_physical(struct intel_plane *plane);
> void intel_plane_init_cursor_vblank_work(struct intel_plane_state *old_plane_state,
> struct intel_plane_state *new_plane_state);
> diff --git a/drivers/gpu/drm/i915/i915_fb_pin.c b/drivers/gpu/drm/i915/i915_fb_pin.c
> index 96ffc4b0d809..a3e5107c12f0 100644
> --- a/drivers/gpu/drm/i915/i915_fb_pin.c
> +++ b/drivers/gpu/drm/i915/i915_fb_pin.c
> @@ -140,16 +140,9 @@ intel_fb_pin_to_ggtt(const struct drm_framebuffer *fb,
>
> atomic_inc(&i915->pending_fb_pin);
>
> - /*
> - * Valleyview is definitely limited to scanning out the first
> - * 512MiB. Lets presume this behaviour was inherited from the
> - * g4x display engine and that all earlier gen are similarly
> - * limited. Testing suggests that it is a little more
> - * complicated than this. For example, Cherryview appears quite
> - * happy to scanout from anywhere within its global aperture.
> - */
> pinctl = 0;
> - if (HAS_GMCH(display))
> + /* PIN_MAPPABLE limits the address to GMADR size */
> + if (intel_plane_needs_low_address(display))
> pinctl |= PIN_MAPPABLE;
>
> i915_gem_ww_ctx_init(&ww, true);

--
Jani Nikula, Intel